I. INTRODUCTION

The Neuromorphic computing systems require synaptic devices capable of analog and linear conductance modulation for accurate weight updates. Although various devices have been proposed as synaptic devices in previous studies, only a few studies have investigated the use of capacitor-less 1 transistor DRAM (1T-DRAM) for synaptic applications ^[1]. Unlike conventional 1 transistor 1 capacitor DRAM (1T1C-DRAM), the 1T-DRAM stores data by retaining holes in the floating body of a single transistor ^{[2- 5]}. Synaptic devices employed in neuromorphic systems must offer high integration density to process large amounts of data in parallel, while also ensuring low power consumption to support the repeated potentiation and depression cycles required during learning. Several emerging nonvolatile memories (eNVMs), such as RRAM, phase-change memory (PCM/PRAM), and MRAM, have been widely investigated as synaptic elements. However, their practical use in online-learning accelerators is often challenged by reliability-related trade-offs, including limited endurance and pronounced spatial/temporal variability that can degrade training stability in large-scale arrays ^[6]. Charge-storage memories such as NAND flash (including 3D NAND) can also be constrained by the relatively high program/erase voltage and latency/energy overhead, together with endurance limitations, depending on the target workload. In contrast, DRAM-type memories inherently provide ultrafast write operation and high endurance, which are attractive for online training with frequent weight updates ^[7]. Nevertheless, conventional 1T/1C DRAM suffers from scalability and density limitations due to the external capacitor. The inherent characteristics of the 1T-DRAM align well with these requirements. Capacitor-less 1T-DRAM concepts eliminate the storage capacitor by storing charge within the transistor body/channel (floating-body charge storage), enabling a simpler cell structure and improved scalability with CMOS-compatible processing ^[1]. Furthermore, to achieve high accuracy in machine learning applications using synaptic devices, it is essential to secure a wide conductance range corresponding to synaptic weights and to ensure that conductance changes occur as linearly as possible. To meet these critical requirements, we propose a graded SiGe body 1T-DRAM as a synaptic device. The device-level characteristics were verified through Sentaurus TCAD simulations, and the system-level performance was evaluated using NeuroSim ^[8].

II. NEUROMORPHIC SYSTEM

Neuromorphic computing aims to emulate the structure and functionality of the human brain to address the inherent limitations of traditional Von Neumann architectures ^[9]. As illustrated in Fig. 1(a), the von Neumann model relies on a strict separation between memory and processing units, which leads to the so-called “von Neumann bottleneck”—a performance limitation due to frequent data shuttling between memory and processor ^[10]. In contrast, the neuromorphic architecture shown in Fig. 1(b) co-locates memory and computation, mimicking the decentralized and parallel structure of biological neural networks ^[11]. In this model, information is processed directly within memory units, akin to how biological synapses simultaneously store and transmit signals ^[12]. A fundamental enabler of this adaptability is synaptic weight, which encompasses processes such as potentiation and depression, both essential for learning and memory formation ^[13]. potentiation strengthens synaptic connections through repeated activation, while depression reduces them, enabling flexible modulation of synaptic weights. In hardware-based learning accelerators, achieving high learning accuracy requires these weight updates to be both linear and symmetric. While many emerging synaptic devices – such as RRAM and PCM – suffer from nonlinear updates that lead to unpredictable weight jumps and poor convergence, improving linearity ensures that conductance changes remain proportional to the applied stimuli. This characteristic is critical for maintaining the precision of gradient-descent paths in deep architectures like Muli-Layer perceptron (MLP) ^[14]. To closely replicate the behavior of biological synapses, artificial synaptic devices must also exhibit additional dynamic properties, such as short-term potentiation (STP), spike-timing-dependent plasticity (STDP), and the ability to realize multi-level conductance states ^[15]. These features are critical for supporting nuanced, time-dependent responses and ensuring fine-grained control over synaptic weights—key elements for building adaptive, brain-inspired computing systems. Integrating these plasticity mechanisms into hardware is essential for achieving real-time learning and energy-efficient processing in neuromorphic platforms ^[14].

Fig. 1. (a) Conventional Von Neumann architecture. (b) Advanced neuromorphic architecture.

III. TUNNELING MODEL CALIBRATION

To calibrate the band-to-band tunneling (BTBT) model using the Sentaurus simulation platform ^[16]planar Si and SiGe tunnel field-effect transistors (TFETs) were fabricated, as illustrated in Fig. 2(a) and 2(b). The Si-based TFET employed source and drain implantation using arsenic under identical conditions on an SOI substrate. In contrast, the SiGe TFET incorporated a 40 nm-thick Si_0.7Ge_0.3 layer grown on a lightly p-doped ($1 \times 10^{15}\text{ cm}^{-3}$) SOI (100) substrate, topped with a Si capping layer. The device further included a 200 nm-thick poly-Si gate and a 3 nm SiO₂ gate dielectric. Both devices featured gate lengths and widths of 400 nm, and their transfer characteristics were evaluated at a drain voltage ($V_{DS}$) of 1.0 V. Kane’s model was employed to calibrate the BTBT generation rate ($G$), which is defined under a uniform electric field as:

where $F_0$ is set to 1 V/m, and $p = 2.5$ for indirect BTBT processes ^[17]. In this expression, $A$ and $B$ are material-dependent fitting parameters, while $F$ denotes the local electric field ^{[18, 19]}. The best fit to the measured Si TFET data yielded $A = 4 \times 10^{14}\text{ cm}^{-1}\cdot\text{s}^{-1}$ and $B = 9.9 \times 10^6\text{ V/cm}$. For the SiGe TFET, the extracted parameters were $A = 3.1 \times 10^{16}\text{ cm}^{-1}\cdot\text{s}^{-1}$ and $B = 7.1 \times 10^5\text{ V/cm}$, demonstrating good agreement between the simulated and measured transfer characteristics. Furthermore, we included Shockley–Read–Hall (SRH) recombination with doping-dependent lifetimes to properly capture recombination effects in heavily doped regions ^[20]. We also utilized a doping-dependent mobility model to account for the reduction in carrier mobility at high impurity concentrations, which was crucial for accurately modeling carrier transport across the SiGe gradient. We also enabled the Multivalley (MLDA) carrier transport model to reflect the multiple conduction band and employed Fermi–Dirac statistics instead of the simpler Maxwell–Boltzmann approximation, as the devices operate in a high-injection regime during write operations. Finally, the effective intrinsic density model was applied without bandgap narrowing, as our simulations focus on the body region where the graded SiGe composition remains within a range that does not necessitate explicit bandgap narrowing modeling. Altogether, these models ensured that the simulation results—particularly the transient behavior of hole storage and conductance modulation—reflect realistic physics in the proposed 1T-DRAM structure.

Fig. 2. Cross-sectional view of the (a) Si TFET; (b) SiGe TFET.

Fig. 3. Calibrated transfer curves of SiGe and Si TFET.

IV. DEVICE STRUCTURE AND ANALYSIS

To improve the learning accuracy of neuromorphic systems employing synaptic devices, it is essential to ensure a wide conductance range that can vary according to the learning process. In the case of a 1T-DRAM, this requires increasing the amount of holes that can be stored in the floating body. To achieve this, the structure proposed in this study utilizes a SiGe body to form a well for hole storage by exploiting the valence band offset between Si and SiGe. In addition, securing good linearity in conduc- tance change the body and drain more difficult. Conse- quently, the conductance variation range decreases simi- larly, during process, as the hole is crucial for enhancing learning accuracy. During repeated potentiation cycles in a 1T-DRAM, the accumulation of holes in the body low- ers the energy band, which makes band-to-band tunneling (BTBT) between concentration in the body decreases the energy band rises, making it harder to extract the stored holes from the well to the drain, which also reduces the conductance variation range. This reduction in conductance modulation during potentiation and depression leads to degraded linearity, which negatively impacts the learning accuracy. To address this issue, we propose a graded SiGe body structure in which the Ge content decreases toward the drain side. Fig. 4 shows the proposed 1T-DRAM-based synaptic device with a graded SiGe body, divided into three segments with decreasing Ge mole fractions (0.3, 0.2, 0.1) from source to drain. In this configuration, holes are mainly stored in the body region near the source. As a result, the energy band near the drain remains less affected during the potentiation and depression processes. This helps maintain a stable and linear conductance change even when potentiation and depression cycles are repeated, thereby improving the learning accuracy of the synaptic device. To evaluate the synaptic behavior of the proposed 1T-DRAM structure, device-level simulations were conducted using the parameters summarized in Tables 1 and 2. Table 1 details the physical design parameters, including gate length, body thickness, and the SiGe composition profile across the body region. To maintain consistency in evaluating synaptic performance across devices with varying Ge content, the read voltage conditions were carefully tailored.

Fig. 4. Schematic of the proposed 1T-DRAM based synaptic device structure with a graded SiGe body.

Fig. 5. Operation processes of the proposed structure: (a) potentiation and (b) depression.

Since a fixed read voltage would produce varying initial drain currents due to composition-dependent threshold voltages, adjustments were made to align the baseline read currents, ensuring a fair assessment of conductance modulation. As shown in Fig. 5(a), during the potentiation operation, a negative gate voltage and a positive drain voltage are applied simultaneously. This biasing condition induces BTBT near the drain-side junction, resulting in hole injection into the body. The injected holes migrate and accumulate primarily in the high-Ge region near the source due to its elevated valence band edge and deeper quantum well. Unlike the conventional structure, in which an increase in hole concentration shifts the entire energy band of the body, thereby suppressing BTBT between the body and the drain, the proposed graded SiGe structure confines most of the holes to the body region adjacent to the source. As a result, BTBT is relatively maintained during the potentiation process. This enables holes to be stored continuously in the body during the repeated potentiation process, thereby ensuring the linear conductance modulation and the wide separation between the minimum conductance ($G_{min}$) and maximum conductance ($G_{max}$) required for accurate and reliable learning in neuromorphic computing. As shown in Fig. 5(b) during the depression operation, a positive gate voltage and negative drain voltage are applied, facilitating hole extraction toward the drain. In the conventional structure, a reduction in hole concentration during the depression process raises the entire energy band of the body, thereby increasing the height of the valence band barrier encountered by holes moving toward the drain, which makes depression difficult. In contrast, in the proposed structure, the barrier height experienced by holes stored in the body is maintained at a relatively constant level, resulting in a more linear conductance change during the depression process. The synaptic weight update was programmed via simultaneous gate and drain voltage pulses, as illustrated in Fig. 6(a) and 6(b) presents the temporal waveform of the gate and drain voltage pulses used to induce BTBT-based programming in the proposed 1T-DRAM synaptic device. Specifically, the drain and gate pulses are applied simultaneously, with a pulse width of 10 ns and a uniform inter-pulse spacing to allow sufficient time for charge stabilization. Fig. 7(a) and 7(b) illustrate the real-time evolution of the drain current as a function of the number of applied programming pulses. This measurement is taken immediately after each BTBT-induced write pulse, thereby capturing the cumulative change in conductance of the proposed 1T-DRAM synaptic device. As observed, the drain current exhibits a monotonic and gradual increase with successive pulses. This behavior directly reflects the incremental accumulation of hole charge within the body region, injected via band-to-band tunneling at the drain–body junction ^[21]. Each individual pulse contributes a discrete quantity of charge, which translates into a measurable increase in channel conductance. The result is a quasi-linear staircase profile, characteristic of analog potentiation behavior. However, simulations indicate that synaptic devices with a uniform SiGe composition across the entire channel—illustrated in Fig. 8(a) for Ge mole fractions of 0.1, 0.2, and 0.3—exhibit rapid conductance saturation and degraded linearity. While a higher Ge content leads to an increased difference between the minimum and maximum conductance values, it also results in accelerated hole accumulation throughout the body, which in turn compromises the linear modulation of conductance. This nonlinearity adversely affects the precision of synaptic weight updates, thereby limiting the learning performance. The corresponding hole density profiles shown in Fig. 8(b)-8(d) further corroborate these findings. As the Ge concentration increases, the body region becomes uniformly saturated with holes, making it difficult to achieve incremental and controllable weight tuning. To address these limitations, a graded SiGe composition profile was introduced, where the Ge content is gradually reduced from source to drain (e.g., Si_0.7Ge_0.3 → Si_0.8Ge_0.2 → Si_0.9Ge_0.1). The potentiation and depression characteristics of this configuration, presented in Fig. 9(a) under identical biasing conditions, demonstrate significantly enhanced linearity compared to uniform counterparts. This improvement is attributed to the spatially engineered charge storage dynamics enabled by the graded composition. Although the reduced BTBT rate in the lower-Ge regions inherently limits the total amount of hole injection, this limitation can be effectively mitigated by increasing the gate voltage during programming ^[22]. Under such conditions, the proposed graded structure is Capable of achieving a wide conductance window while maintaining excellent linearity. This observation implies that, even with enhanced hole injection, the device can preserve its analog modulation characteristics due to the spatial confinement and asymmetric energy barriers inherent to the graded profile. As further evidenced in Fig. 9(b), the graded body structure promotes localized hole accumulation near the high-Ge source region, forming a stable charge reservoir and suppressing back-diffusion. This not only enhances charge retention and reduces variability but also enables the realization of multiple, well-separated conductance states. These results strongly suggest that the proposed device architecture is highly promising for neuromorphic systems, offering both linear and high-resolution weight modulation—key attributes for achieving superior recognition performance in neural network applications.

Fig. 6. (a) Potentiation voltage pulses and (b) depression voltage pulses.

Fig. 7. Read current evolution following each (a) potentiation pulse and (b) depression pulse.

Fig. 8. (a) Potentiation and depression curves for SiGe body with varying Ge content. (b)-(d) corresponding hole density profiles for each uniform composition after 20 and 60 potentiation cycles.

Fig. 9. (a) Potentiation and depression curves of the graded SiGe body. (b) Hole density profile of the graded body in 20 and 60 potentiation cycles.

V. IMAGE RECOGNOTION ACCURACY

To assess the learning and inference capabilities of the proposed synaptic device, we employed a multilayer perceptron (MLP) neural network simulation using NeuroSim V3.0. The network architecture consists of 400 input neurons, 100 hidden neurons, and 10 output neurons, as illustrated in Fig. 10(a). The input layer processes $20\times 20$-sized MNIST handwritten digit images, with classification into 10 numerical classes (0–9). A total of 60,000 training samples and 10,000 test samples were used to evaluate synaptic learning performance ^[13]. Fig. 10(b) shows how a single layer in Fig. 10(a) can be implemented using a synaptic crossbar array. The input activations are applied as voltages along the row lines, and each cross-point cell stores a programmable conductance that represents the synaptic weight between an input node and an output node. The currents collected on each column naturally sum the contributions from all input rows, producing the weighted-sum output of a fully connected layer. Accordingly, the 400-to-100 connection in can be mapped to a $400 \times 100$ synaptic array as illustrated in Fig. 10(b). In neuromorphic systems, synaptic plasticity is typically realized through potentiation and depression, where the conductance of the synaptic device should ideally change linearly with the number of input pulses ^[23]. However, in practice, most emerging memory-based Synaptic devices—including our proposed 1T-DRAM synapse—exhibit non-linear weight update behavior. This deviation leads to a mismatch between the desired and actual conductance states, which can compromise learning accuracy ^[17]. To model this behavior, we adopt a generalized exponential model that describes conductance modulation during potentiation and depression as a function of the number of pulses as follows:

where $G_{LTP}$ and $G_{LTD}$ are the conductance for potentiation and depression, respectively, and $P$ is number of pulses. As shown in Fig. 8, where $G_{max}$, $G_{min}$, and $P_{max}$ are experimentally extracted parameters, and $A$ governs the degree of nonlinearity ^[9]. This model is used to fit the experimentally observed conductance behavior of our device, and nonlinearity values of potentiation and depression ($NL_{LTP}$ and $NL_{LTD}$) are extracted to quantify linearity. Lower absolute values of NL indicate better linearity, which is crucial for reliable synaptic learning ^[24]. As demonstrated in Fig. 11(a), the proposed graded-body synaptic device achieves improved linearity under enhanced gate voltage conditions. A total of 60 potentiation and 60 depression pulses were applied, and the resulting drain current exhibits a smooth, near-linear increase during potentiation, followed by symmetric depression. This behavior confirms the device’s ability to support analog, symmetric weight updates, which are essential for training accuracy ^{[25, 26]}. Fig. 11(b) shows the hole density distribution in the body region of the proposed device after 20 and 60 potentiation cycles. Owing to the graded SiGe profile, holes are predominantly stored in the source-side Si_0.7Ge_0.3 region, and the sustained BTBT during the potentiation process enables a continuous increase in hole concentration until 60 potentiation cycles, reaching a peak density of $1.98 \times 10^{19}\text{ cm}^{-3}$. This efficient hole storage mechanism prevents early saturation of conductance and facilitates the realization of a wide and linear conductance window. To benchmark the system-level performance of the proposed synaptic device, recognition accuracy was evaluated using the electrical and structural parameters, as summarized in Table 3. Regarding the selection of operating bias conditions, the voltages were carefully optimized based on the physical characteristics of the proposed graded SiGe body. Due to this structural asymmetry, the BTBT process, which governs hole injection from the drain during write operations, is significantly influenced by the local Ge concentration. Specially, the lower Ge content near the drain reduces the BTBT rate compared to the source side. To ensure that a sufficient volume of holes is injected and retained within the body reservoir, we fixed the drain voltage to stabilize the BTBT ratio and swept the gate voltage to precisely control the amount of accumulated charge. The selected optimized gate voltage range was determined to maximize the conductance modulation window while maintaining stable injection dynamics. In addition, Table 4 presents the fitting parameters used in the configuration for NeuroSim simulations. These include nonlinearity coefficients for both potentiation and depression, where the graded SiGe body structure demonstrates superior linearity compared to uniform SiGe body configurations. This numerical evidence underscores the device’s enhanced capability for accurate weight modulation. Fig. 11(c) illustrates normalized conductance responses of the proposed structure fitted to NeuroSim’s nonlinearity model. These curves highlight that the graded SiGe structure exhibits more linear conductance progression than the conventional uniform SiGe body structures, which is critical for accurate learning in neuromorphic networks. Furthermore, Fig. 12 presents the recognition accuracy results obtained using three device types: uniform SiGe body structures with Ge fractions of 0.1 and 0.2, and the proposed graded SiGe device under identical bias conditions, and the graded device under an enhanced gate voltage of −3.3 V, which yielded the best overall performance Notably, the device with a uniform Ge content of 0.3 was excluded from the accuracy evaluation due to its severely degraded linearity, which makes it unsuitable for use as a synaptic device. The proposed device achieved a peak recognition accuracy of 84.9%, with average accuracy of 73.61%. These results clearly demonstrate the advantage of the graded SiGe profile in delivering both high linearity and wide dynamic range—two essential properties for achieving reliable and accurate recognition in neuromorphic applications ^[24].

Fig. 10. (a) MLP (Multilayer Perceptron) network utilized for image recognition, (b) Synaptic array configuration.

Fig. 11. (a) Potentiation/depression curves of the graded SiGe synaptic device, (b) Hole density of the graded SiGe synaptic device after 20 and 60 potentiation cycles, (c) Normalized conductance of graded body.

Fig. 12. Recognition accuracy comparison between uniform SiGe body devices and the proposed graded SiGe body structure.

VI. PROCESS FLOW

To achieve high integration density while enabling controllable formation of a compositionally engineered SiGe body, a vertically oriented channel architecture on a bare silicon wafer is adopted. The device fabrication begins on a bare silicon wafer where a common source region is first defined by n⁺ implantation and activation annealing. To form the charge-storage body, epitaxial growth of SiGe is performed on the source region while gradually tuning the Ge fraction to create a vertically graded composition. This graded SiGe stack enables controlled band engineering within the body region (Fig. 13 (a)). Next, a hard mask is patterned and anisotropic dry etching is carried out to define vertical channel pillars extending down to the common source (Fig. 13(b)). After pillar formation, a gate dielectric layer is grown along the vertical channel. A conductive gate layer is then deposited, followed by anisotropic etch-back to leave the gate material on the sidewalls, thereby forming the word line through a spacer-based sidewall technique (Fig. 13(c)). Finally, metal patterning process is performed to establish the drain lines (bit lines), completing the vertical 1T-DRAM structure with a graded SiGe body (Fig. 13(d)).

Fig. 13. (a) Epitaxial growth of a vertically graded SiGe body on the common source region. (b) Definition of vertical channel pillars through lithography and anisotropic dry etching. (c) Formation of the gate stack by gate dielectric growth followed by sidewall spacer-based gate (word line) creation. (d) Drain contact metal patterning to establish the bit line interconnection.

VII. CONCLUSIONS

In this work, we proposed a 1T-DRAM structure with graded SiGe channel for synaptic devices and demonstrated its superiority over conventional uniform SiGe body configurations in terms of linearity and conductance modulation. In uniform SiGe body structures (e.g., Si_0.9Ge_0.1, Si_0.8Ge_0.2, Si_0.7Ge_0.3), hole accumulation occurs uniformly throughout the body during the potentiation operation. This results in rapid and nonlinear increases in conductance during repeated pulses, ultimately breaking the linearity required for accurate weight updates. Moreover, the conductance window (G_max – G_min) degrades over successive potentiation cycles, limiting learning accuracy and reliability. In contrast, the proposed device utilizes a spatial gradient in the SiGe composition (e.g., Si_0.7Ge_0.3 near the source to Si_0.9Ge_0.1 near the drain), which enables selective hole confinement and improved conductance linearity. Even under strong write conditions (–3.3 V gate bias), the device maintains excellent linearity while achieving a wide conductance range. As a result, the proposed structure effectively overcomes the key limitations of conventional uniform SiGe body devices and offers a promising solution for high-performance neuromorphic systems with enhanced learning accuracy and device reliability.