Design and Implementation of 3D FeNAND Array Interface Circuit for Compute-in-Memory
Applications
Young-Jun Yu1
Jihoon An2
Ik-Jae Kim3
Jaehyun Ko2
Byungsub Kim2
Jang-Sik Lee3
Dong-Woo Jee1,4,*
-
Department of Intelligence Semiconductor Engineering, Ajou University, Suwon, 16499,
Korea
-
Department of Electrical Engineering, POSTECH, Pohang, 37673, Korea
-
Department of Materials Science and Engineering, POSTECH, Pohang, 37673, Korea
-
Department of Electrical and Computer Engineering, Ajou University, Suwon 16499, Korea.
E-mail : dwjee@ajou.ac.kr
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index terms
Compute-in-Memory (CIM), 3D FeNAND array, interface circuit, high voltage (HV) driver, source-line (SL) driver, word-line (WL) driver, multiply-and-accumulate (MAC)
I. INTRODUCTION
Compute-in-memory (CIM) has recently gained significant attention as a key solution
for enhancing the computational efficiency of artificial intelligence (AI) computation.
In conventional von Neumann architectures, the data movement between the processing
unit and memory leads to data bottlenecks, limiting computational speed and energy
efficiency [1-
3]. In contrast, CIM structures enable multiply-and-accumulate (MAC) operation, which
accounts for the largest portion of AI computations, to be performed directly within
memory cells. This approach reduces data transfers between memory and processors,
thereby contributing to significant savings in both power and time [4,
5]. Due to these advantages, CIM has emerged as a promising alternative for AI applications
that require high-speed, low-power, and large-scale parallel computations.
To implement CIM-based MAC operations, various memory technologies, such as phase-change
memory and resistive-switching memory have been widely studied [4,
6,
7]. However, these types of memories are limited to storing a single weight value per
memory cell, leading to an increase in chip size for large-scale parallel MAC operations.
In contrast, ferroelectric (Fe) memory offers several advantages, such as multi-level
weight storage within a single memory cell [8]. Additionally, it is CMOS compatible, allowing the use of existing memory technologies,
and its capability for 3D stacking enables high-density integration without increasing
the chip size [9-
11].
Fig. 1 shows the concept of MAC operation based on 2×3 3D FeNAND [9]. In this structure, weights are stored in each memory cell, and the input vectors
$X_{0-2}$ are applied through the word lines (WL). As a result, the multiplication
of weight and input values is represented by the on-resistance of each cell. When
a constant voltage difference is applied between the bit lines $\text{BL}_{0-1}$ and
the source line SL, the MAC result appears as the source line current $I_{\text{SL}}$,
which is determined by the combined on-resistance of the selected cells. By simultaneously
selecting multiple bit lines and tying their source lines together, parallel MAC operations
can be performed [10,
12].
Fig. 1. Compute-in-memory concept with 2×3 3D FeNAND array.
However, many prior studies have focused on device-level demonstrations [8,
9] or high-level architectural research [10,
11,
13,
14], while the interface circuits required to drive Fe devices for CIM operation remain
largely unexplored. Additionally, to achieve a wide memory window for multi-level
operation, the Fe devices require high operating voltage, which complicates interfacing
them with low-voltage CMOS circuits.
In this work, we present an FeNAND array interface circuit for CIM applications [15] that supports both high-voltage driving of memory devices for a wide memory window
and interfacing with low-voltage CMOS logic circuits. The paper is organized as follows.
Section II describes the 8×3 3D FeNAND array interface chip architecture and its building
block design. Section III presents the measurement results, and Section IV concludes
this paper.
II. CIRCUIT DESCRIPTION
1. Proposed 8×3 3D FeNAND Array Interface Chip
Fig. 2 shows the proposed interface chip architecture for 3D FeNAND array-based CIM applications.
Although this chip is designed for an 8×3 array, its architecture is inherently scalable
and can be readily adapted to larger array sizes. To apply the bit line voltages $V_{\text{BL}0\text{-}5}$,
six high-voltage (HV) drivers are used. For the WL voltages $V_{\text{WL}0\text{-}2}$,
five HV drivers generate five distinct analog voltages, which are applied to the input
of analog multiplexers (MUXes). Through the selection operation of each WL MUX, the
desired voltage is transferred to $V_{\text{WL}0\text{-}2}$. Because the WL voltage
continuously changes to apply input vectors during CIM operation, the required voltages
are pre-generated and then delivered through a MUX, allowing the settling time to
be minimized. Two source-line (SL) drivers generate the $V_{\text{SL}0\text{-}1}$.
Each SL driver independently senses the corresponding memory-cell current $I_{\text{SL}0\text{-}1}$,
converts it into the low voltage output $V_{\text{CIM_OUT}0\text{-}1}$. These output
voltages represent the outcome of the MAC operation. In summary, the proposed interface
chip architecture enables flexible WL, BL, and SL voltage control and SL current readout
for CIM operation.
Fig. 2. Top architecture of 8×3 3D FeNAND array interface chip.
Each building block needs to meet the specific requirements of the target 3D FeNAND
devices for CIM operation [8,
9]. The HV driver should generate a wide voltage range for multi-level operation of
each memory cell. The SL driver should not only process ultra-low currents (100 pA–100
nA), considering the on/off current range of the target memory device, but also tolerate
a wide input voltage ($V_{\text{SL}}$) range. The WL MUX must achieve a short transition
time for the fast input-vector updates during CIM operation. The detailed implementations
of each circuit block are described in the following subsections.
2. High Voltage (HV) Driver Circuit
The circuit schematic of the HV driver is shown in Fig. 3. In this structure, 30 V high voltage supply $V_{\text{HV}}$ is used to generate
a wide output voltage range from 3 V to 26 V. When the output voltage $V_{\text{DRV}}$
is at its lowest level of 3 V, the drain-source voltage across the pass transistor
$M_{\text{PASS}}$ reaches approximately 27 V. Therefore, a high-voltage PMOS transistor
with $|V_{\text{DS}}|_{\text{MAX}}$ of 29 V is used for $M_{\text{PASS}}$. Since $|V_{\text{GS}}|_{\text{MAX}}$
of $M_{\text{PASS}}$ transistor is limited to 5 V, the HV gate control stage composed
of the error amplifier, $M_0$, $R_1$, and $R_2$ drives the gate of $M_{\text{PASS}}$.
The regulated output voltage $V_{\text{DRV}}$ is determined by the reference voltage
$V_{\text{REF}}$ and the resistive feedback network consisting of $R_3$, $R_{\text{EQ_C}}$,
and $R_{\text{EQ_F}}$ as follows.
In (1), $V_{\text{REF}}$ is 1V, and $R_3$ is 2.5 MΩ. To dynamically control the output voltage
$V_{\text{DRV}}$ during CIM operation, both $R_{\text{EQ_C}}$ and $R_{\text{EQ_F}}$
are implemented as variable resistors using R-2R DAC structure, which enables digital
code-controlled adjustment.
Fig. 3. Circuit diagram of High Voltage (HV) driver.
Fig. 4. Circuit diagram of Coarse R-2R DAC (top), Fine R-2R DAC (bottom).
Fig. 4 shows the structure of current steering R-2R DACs controlled by the 6-bit Coarse
and Fine input codes, respectively. The DAC’s output voltage $V_{\text{FB}}$ is maintained
at 1V by the closed-loop feedback of the HV driver. In this condition, by adjusting
each DAC’s output current $I_{\text{OUT_C}}$ and $I_{\text{OUT_F}}$ by controlling
Coarse and Fine codes, the equivalent resistances $R_{\text{EQ_C}}$ and $R_{\text{EQ_F}}$
can be controlled. In each DAC, 200 kΩ of unit resistance R is used. When both the
6-bit Coarse and Fine codes are all set to maximum value, all switches are turned
off, disconnecting the DACs from all current sources. In this state, both $R_{\text{EQ_C}}$
and $R_{\text{EQ_F}}$ become 200 kΩ, resulting in a parallel resistance $R_{\text{EQ_C}}\parallel
R_{\text{EQ_F}}$ of 100 kΩ. Consequently, the output voltage $V_{\text{DRV}}$ becomes
$1 + 2.5\text{ M}\Omega/100\text{ k}\Omega = 26\text{ V}$, as determined by (1). By decreasing the coarse and fine code of each DAC by 1 LSB, the output current
$I_{\text{OUT_C}}$ and $I_{\text{OUT_F}}$ decrease by $I_{\text{unit}}/32$ and $(I_{\text{unit}}/10)/32$,
respectively. Consequently, the output voltage $V_{\text{DRV}}$ decreases in proportion
to the DAC input code, enabling coarse-tuning and fine-tuning of $V_{\text{DRV}}$.
It should be noted that both the voltage resolution and the output range of $V_{\text{DRV}}$
can be freely adjusted as required by changing $I_{\text{unit}}$. For example, when
$I_{\text{unit}}$ is 4.27 μA and $I_{\text{unit}}/10$ is 427 nA, a 1-LSB decrease
in the coarse code reduces $I_{\text{OUT_C}}$ by approximately 133 nA, resulting in
a $V_{\text{DRV}}$ decrease of 350 mV. Similarly, a 1-LSB change in the fine code
yields a ten-times smaller voltage step of 35 mV. In this example, the output voltage
$V_{\text{DRV}}$ can vary from 3 V to 26 V.
The output pass transistor sources current into the output, allowing the output voltage
$V_{\text{DRV}}$ to settle within 300 μs under a 200 pF load condition for the maximum
low-to-high input code change. On the other hand, when the input code decreases, $V_{\text{DRV}}$
only decreases by the RC discharging through the resistive path $R_3+(R_{\text{EQ_C}}\parallel
R_{\text{EQ_F}})$, resulting in a relatively long settling time. To reduce the settling
time during $V_{\text{DRV}}$ decrease control, a pull-down control block is added,
as shown in Fig. 5. The error amplifier’s output $V_{\text{EA}}$ of the HV driver is connected to the
inverting input of the amplifier in the pull-down control block. During no pull-down
operation condition ($V_{\text{PULLDN}} = 0$), $V_{\text{EA}}$ stays between 0.8 V
and 1 V, causing $V_{\text{AMPOUT}}$ to remain high (5 V). The 6-bit comparator detects
whether the 6-bit coarse code has decreased by comparing the present code (input A)
and the previous code (input B) stored in a D-Flip-Flop (DFF) at the rising edge of
the clock. If A<B, the comparator’s output $V_{\text{COMP}}$ becomes logic high (5
V), which also drives $V_{\text{PULLDN}}$ high, turning on the pull-down transistor
$M_{\text{PULLDN}}$ to rapidly discharge $V_{\text{DRV}}$. As the pull-down operation
proceeds, the feedback voltage $V_{\text{FB}}$ drops below the reference voltage $V_{\text{REF}}$
(1 V), increasing $V_{\text{EA}}$. Once $V_{\text{AMPOUT}}$ is below the logic threshold,
the inverter’s output toggles from low to high, triggering the reset (RST) signal
of the DFF. The reset clears the stored coarse code, forcing $V_{\text{COMP}}$ and
$V_{\text{PULLDN}}$ to return to logic low, thereby terminating the pull-down operation.
At the next rising edge of the clock, the DFF captures a new coarse code value, and
the comparator resumes comparison between the present and previous codes, enabling
successive pull-down control cycles.
Fig. 5. Circuit diagram of pull-down control block.
Fig. 6. Post-layout transient simulation result of HV driver with pull down control
on (top) and off (bottom).
Fig. 6 shows the post-layout simulation results of the HV driver. As the 6-bit coarse code
increases by 1 LSB, the output voltage $V_{\text{DRV}}$ changes with a resolution
of approximately 350 mV from 3 V to 26 V. When the code decreases from its maximum
to minimum value, the pull-down control is activated, which greatly improves the settling
time from 15.5 ms to 94 μs.
3. Source Line (SL) Driver
Fig. 7 shows the circuit schematic of the SL driver. The HV driver controls $V_{\text{SL_C}}$
through the coarse and fine input codes, and the resulting source-line voltage $V_{\text{SL}}$
is formed at $V_{\text{SL_C}}+0.5\text{ V}$, serving as the source-line voltage for
the 3D FeNAND array. The transistor $M_{\text{BUF}}$ not only boosts the output impedance
for $I_{\text{SL}}$ but also decouples the effect of $V_{\text{SL}}$ change to $V_{\text{CIM_OUT}}$.
In this work, $V_{\text{BP}}$ of 4.5 V is used to keep the $V_{\text{BPD}}$ to 5 V.
Both $M_{\text{SL_C}}$ and $M_{\text{BUF}}$ operate in the subthreshold region to
minimize the $|V_{\text{GS}}|$ change over $I_{\text{SL}}$’s ultra-low current range
from 100 pA to 100 nA.
Fig. 7. Circuit diagram of Source-Line (SL) driver.
Fig. 8. Simulation results of SL driver’s VSL and VCIM_OUT versus ISL.
For $V_{\text{CIM_OUT}}$ generation, the transimpedance resistor $R_{\text{TI}}$ is
added. With $R_{\text{TI}}$ of 10 MΩ, the memory current $I_{\text{SL}}$ ranging from
100 pA to 100 nA is converted into an output voltage $V_{\text{CIM_OUT}}$ ranging
from 0.1 mV to 1 V, which is suitable for interfacing low-voltage CMOS signal processing
circuits.
Fig. 8 shows the simulation results of SL driver. $V_{\text{SL}}$ change remains less than
300mV across the entire target current range, even under wide-range variations of
$V_{\text{SL_C}}$. $V_{\text{CIM_OUT}}$ increases linearly with $I_{\text{SL}}$, demonstrating
accurate current-to-voltage conversion over the full operating range.
4. Word Line (WL) MUX
Fig. 9 shows the overall architecture of the WL MUX, which is composed of four main blocks:
Bidirectional switches, charge pumps, level shifters and a decoder. The WL MUX selects
one of five analog input voltages, $V_{\text{IN}1\text{-}5}$ and transfers it to the
output $V_{\text{OUT}}$. $V_{\text{IN}1}$ receives the lowest among the predefined
voltages for WL driving, while $V_{\text{IN}5}$ receives the highest. The bidirectional
switch structure [16] keeps the reverse bias of the body-drain diode of the mux switches to prevent any
undesired short circuit current among input voltages. The charge pump block generates
high supply voltage of $V_{\text{H}1\text{–}5}$ and $V_{\text{HO}}$ for the level
shifter from $V_{\text{IN}1\text{–}5}$ and $V_{\text{OUT}}$. The level shifters generate
high voltage gate control signals from the low voltage decoder output $\text{LS}_{\text{IN}1\text{–}9}$.
Fig. 9. Top diagram of WL MUX.
The detailed circuit schematic of the charge pump is shown in the upper part of Fig. 10. During each rising edge of CLK, the intermediate node $V_{\text{M}}$ is boosted
and transfers charge through the diode to the $V_{\text{H}}$ node, where the storage
capacitor $C_{\text{S}}$ accumulates the transferred charge. The diodes are implemented
with the gate-source connected transistors, and the $V_{\text{H}}$ is approximately
3.5 V higher than $V_{\text{L}}$. The detailed schematic of the level shifter is shown
in the lower part of Fig. 10. The low voltage (0/5 V) logic state is shifted to $V_{\text{H}}$ or $V_{\text{L}}$
through the capacitive coupling with the floating latch.
Fig. 10. Circuit diagram of charge pump (top) and level shifter (bottom).
Fig. 11. WL MUX decoder truth table.
A key characteristic of the bidirectional MUX structure is that the intermediate node
$V_{\text{D}}$ is floated when $V_{\text{OUT}}$ is lower than $V_{\text{IN}}$, preventing
current flow from $V_{\text{OUT}}$ to unselected $V_{\text{IN}}$. Fig. 11 illustrates the detailed decoding logic that generates the $\text{LS}_{1\text{–}9}$
control signals. For instance, when $V_{\text{IN}3}$ is selected as the output, $V_{\text{D}2}$
and $V_{\text{D}3}$ are biased to $V_{\text{OUT}}$, while $V_{\text{D}4}$ and $V_{\text{D}5}$
are floated.
III. IMPLEMENTATION RESULT
The proposed interface circuits were fabricated using an 180 nm BCD process, and the
chip microphotograph is shown in Fig. 12. Fig. 13 shows the measurement results of single HV driver output $V_{\text{DRV}}$ for each
coarse/fine code. The result successfully demonstrates that HV drivers support wide
voltage range with fine control for multi-level operation of the target memory cell.
Fig. 13 also shows the transient response of the six HV drivers for $V_{\text{BL}0\text{-}5}$
generation. Each HV driver generates $V_{\text{BL}0\text{-}5}$ independently through
dedicated coarse/fine control code. The fast pull-down operation is also well confirmed.
The settling time was measured to be 245 μs for the maximum low-to-high transition
(3 V → 26 V) and 132 μs for the high-to-low transition (26 V → 3 V) with 200 pF load.
Fig. 12. Chip microphotograph.
Fig. 13. Measured VDRV with Coarse/Fine control (left) and transient response of VBL0-5
(right).
Fig. 14. Measurement setup (left) and measured transient response of SL driver (right).
Fig. 14 shows the combined measurement results of the BL driver and the SL driver. The FeFET
device is modeled as a resistor $R_{\text{FeFET}}$ and connected between the BL-driver
output ($V_{\text{BL}}$) and the SL-driver input ($V_{\text{SL}}$). After fixing $V_{\text{SL}1}$
and $V_{\text{SL}2}$ at 8.1 V, $V_{\text{BL}1}$ and $V_{\text{BL}2}$ were swept from
8.1 V to 9.35 V in 30 mV steps. Given that $R_{\text{FeFET}} = 12.5\text{ M}\Omega$,
the generated current ranges from 0 to 100 nA. Then this current is converted to a
voltage through a parallel equivalent resistance of 5 MΩ, consisting of the 10 MΩ
$R_{\text{TIA}}$ and the 10 MΩ probe resistance, resulting in $V_{\text{CIM_OUT}1}$
and $V_{\text{CIM_OUT}2}$ varying from 0 to 500 mV according to the change in $V_{\text{BL}1}$
and $V_{\text{BL}2}$.
Fig. 15 shows the measured transient response of WL MUX. HV drivers generate five WL voltages
of 3 V, 5 V, 7 V, 10 V, and 12 V. Three WL MUXes share HV driver outputs as their
$V_{\text{IN}1\text{–}5}$ inputs. By controlling 3-bit SEL inputs of each WL MUX,
the word-line voltages $V_{\text{WL}0\text{-}2}$ are successfully generated. Fig. 16 presents the measured WL-voltage rise and fall times for different load capacitances,
with a maximum rise/fall time of 70.31 ns observed at a load capacitance of 200 pF.
Fig. 15. Measured transient response of WL MUXes with SEL control.
Fig. 16. Measured rise time (left) and fall time (right) of WL MUX versus load capacitance
CL.
Fig. 17. Measured VBL0–5, VSL0–1 and VWL0–2 of the interface chip for exemplary erase,
program, and read operation of the [1,0] FeFET device in the 8x3 array in Fig. 2.
Fig. 17 shows measured $V_{\text{BL}0\text{–}5}$, $V_{\text{SL}0\text{–}1}$ and $V_{\text{WL}0\text{–}2}$
of the interface chip for exemplary erase, program, and read operation of the [1,0]
FeFET device in the 8×3 array in Fig. 2. One operation cycle consists of erase, program, and read phases, each separated
by a standby phase. During the standby phase, all BLs and SLs are biased at 8V, while
all WLs are biased at $V_{\text{STB}} = 5\text{ V}$. In the erase phase, the target
WL is driven with $V_{\text{ERS}} = 3\text{ V}$, and the remaining WLs are biased
with $V_{\text{PASS}} = 10\text{ V}$. To prevent erase disturbance on adjacent cells,
$V_{\text{inhibit}} = 10.4\text{ V}$ is applied to $V_{\text{BL}1\text{–}3}$. In the
program phase, the target WL is driven with $V_{\text{PROG}} = 12\text{ V}$, with
$V_{\text{PASS}} = 10\text{ V}$ applied to the other WLs, and program inhibit voltage
is applied to adjacent BLs. In the read phase, the target WL is biased at $V_{\text{READ_WL}}
= 7\text{ V}$, while the others remain at $V_{\text{PASS}} = 10\text{ V}$. For the
CIM operation, $V_{\text{BL}0}$ is driven to $V_{\text{SL}0} + 0.3\text{ V}$ to generate
the read current, while the remaining BLs are held at the $V_{\text{SL}1}$ to suppress
current flow. The resulting current is converted into an output voltage $V_{\text{CIM_OUT}}$
through the SL driver’s transimpedance resistor. Table 1 summarizes the performance of the implemented chip and its sub blocks.
Table 1. Performance summary of proposed interface chip.
|
Chip feature
|
|
Process
|
180 nm BCD
|
|
Area
|
5 mm × 3.7 mm
|
|
Output
|
$V_{\text{BL}0-5}$, $V_{\text{WL}0-2}$, $V_{\text{SL}0-1}$, $V_{\text{CIM_OUT}0-1}$
|
|
Supply
|
30 V, 5 V (Internal Logic Circuits), 1 V (CMOS interface)
|
|
|
Sub-blocks
|
|
HV driver
|
SL driver
|
WL MUX
|
|
Power
|
268 μW
|
268 μW
|
2 nW
|
|
Area
|
0.93 mm × 0.37 mm
|
1 mm × 0.3 mm
|
0.7 mm × 1.8 mm
|
|
Control
|
Coarse (6b)/ Fine (6b)
|
Coarse (6b)/ Fine (6b)
|
3b
|
|
Input
|
-
|
7 V–26.5 V / 100 pA–100 nA
|
3 V–12 V (five inputs)
|
|
Output
|
3 V–26 V / Max 100 μA
|
0 V–1 V
|
3 V–12 V
|
|
Rise / Fall timeMAX
|
245 μs / 132 μs @ 200 pF load
|
-
|
70.31 ns / 69.7 ns @ 200 pF load
|
IV. CONCLUSIONS
An 8×3 3D FeNAND array interface chip that supports both high-voltage driving of the
devices and interfacing with low-voltage CMOS logic circuits for CIM applications
is presented. The HV driver generates output voltage from 3 V to 26 V using digitally
controlled R-2R DAC based structure, and the pull-down control technique reduces settling
time for faster CIM operation. The SL driver provides the SL driving voltage and converts
ultra-low current to output voltage for the low-voltage CMOS circuits. The WL MUX
selects one of five analog voltages and transfers it to output with a rise/fall time
under 100 ns, enabling 10 MHz of input vector updates during CIM operation.
ACKNOWLEDGMENTS
This work was supported by the NRF of Korea under Grants RS-2026-25539124 and 2022M3H4A1A03067131.
The EDA Tools were supported by IDEC.
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Young-Jun Yu received his B.S. degree from the Department of Electrical and Computer
Engineering from Ajou University, Korea, in 2023. He is currently pursuing an M.S.
degree in the Department of Intelligence Semiconductor Engineering at Ajou University.
His research interests include high voltage driver circuits for AI and biomedical
applications.
Jihoon An received the B.S. degree from the School of Electrical Engineering and Computer
Science, Gwangju Institute of Science and Technology (GIST), in 2024. He is currently
pursuing an M.S. degree with the Department of Electrical Engineering at the Pohang
University of Science and Technology (POSTECH), Pohang, South Korea. His current research
interests include analog-to-digital converters and in-memory computing system.
Ik-Jae Kim received his B.S. degree from Kyung Hee University (2018) and a Ph.D. degree
from POSTECH (2024), South Korea. He is currently a staff engineer at Samsung Electronics.
His research interests focus on next-generation memories and neuromorphic devices
based on hafnia-based ferroelectrics.
Jaehyun Ko received the B.S. degree in electronic and communication engineering from
Hanyang University (ERICA Campus), Ansan, South Korea, in 2017. He is currently pursuing
an M.S. degree in electrical engineering with the Pohang University of Science and
Technology (POSTECH), Pohang, South Korea. His current research interests include
delta-sigma modulator and high-speed link circuit.
Byungsub Kim received the B.S. degree in electrical engineering from the Pohang University
of Science and Technology (POSTECH), Pohang, Korea, in 2000, and the M.S. and Ph.D.
degrees in electrical engineering and computer science from the Massachusetts Institute
of Technology (MIT), Cambridge, MA, USA, in 2004 and 2010, respectively. He was an
Analog Design Engineer at Intel Corporation, Hillsboro, OR, USA, in 2010 and 2011.
In 2012, he joined the faculty of the Department of Electrical Engineering at POSTECH,
where he is currently a Professor. Dr. Kim has received several prestigious awards.
He was the recipient of the 2009 IEEE Journal of Solid-State Circuits Best Paper Award
and the Analog Devices Inc. Outstanding Student Designer Award in 2009. He was also
a co-recipient of the Beatrice Winner Award for Editorial Excellence at the 2009 IEEE
International Solid-State Circuits Conference. For several years, he served as a Technical
Program Committee member of the IEEE International Solid-State Circuits Conference
and is currently serving as the Wireline TPC Subcommittee Chair of the IEEE Asian
Solid-State Circuits Conference. His current research interests include analog layout
generation, analog circuit optimization, and high-speed link design. His research
group developed pLay, a framework for analog layout generation.
Jang-Sik Lee received his B.S., M.S., and Ph.D. degrees in materials science and engineering
from Seoul National University, Korea in 1997, 1999, and 2002, respectively. In 2002,
he joined the Los Alamos National Laboratory as a director’s postdoctoral fellow.
In 2004, he joined the memory division of Samsung Electronics as a senior research
engineer. He was a professor at Kookmin University from 2006 to 2013. In 2013 he joined
Pohang University of Science and Technology (POSTECH), Korea, where he is currently
a Professor in the Department of Materials Science and Engineering/Department of Semiconductor
Engineering and Mueunjae Chair Professor. His research interests include next-generation
memory and neuromorphic devices using emerging materials and processes.
Dong-Woo Jee received the B.S., M.S., and Ph.D. degrees in electronic and electrical
engineering from the Pohang University of Science and Technology, Pohang, South Korea,
in 2006, 2009, and 2013, respectively. From 2011 to 2012, he was a Visiting Researcher
with the University of Michigan, Ann Arbor, MI, USA. From 2013 to 2015, he was an
Analog IC Designer with the Biomedical Circuit group, imec, Leuven, Belgium. In 2015,
he joined Ajou University, Suwon, South Korea, where he is currently a professor.
From 2021 to 2022, he was a visiting scholar with Arizona State University, Tempe,
AZ, USA. His research interests include circuit techniques for analog/digital frequency
synthesizer phase-locked loop, ultra-low power clock generation for sensor node system,
sensor interface circuits, in-sensor computing, and mixed signal circuits for biomedical
applications. Dr. Jee was a recipient of the Gold Prize at the 17th HumanTech Paper
Award hosted by Samsung Electronics in 2011.