I. INTRODUCTION

An impulse-radio pulse width modulation (IR-PWM) based wireless data acquisition system, which encodes analog information in the form of pulse width and transmits it as impulses, was proposed ^[1]. In the system, a high-resolution time-to-digital converter (TDC) with a high sampling rate is necessary to accurately reconstruct the encoded signal. While conventional systems have used high-speed oscilloscopes or ADC-FPGA platforms for pulse width measurement, such approaches face limitations in memory to extend the system as real-time communication.

As shown in Fig. 1, this work focuses on the design of a dedicated TDC that directly digitizes the recovered PWM signals. By replacing the external measurement instruments with an integrated TDC, the proposed approach enables precise pulse width digitization and demonstrates the TDC as an essential component for practical implementation.

Fig. 1. Conceptual illustration of the proposed TDC-based monitoring system for IR-PWM pulse width measurement in CMUT-based ultrasound imaging.

Moreover, existing TDC designs reported in the literature are not suitable for IR-PWM applications due to insufficient resolution, or limited adaptability to sub-nanosecond pulse tracking.

In particular, the IR-PWM system requires a TDC with at least 10 MS/s conversion rate and timing accuracy better than 24 ps ^[1]. However, previously reported designs fail to meet these specifications. For example, the three-step cyclic Vernier TDC ^[2] achieves a resolution of 36–135 ps with a maximum conversion rate of 1.86 MS/s, which is insufficient in both resolution and speed. The $256\times$ cyclic interpolator TDC array ^[3] provides 20 ps resolution but is limited to 0.17 MS/s, falling short of the required throughput by more than two orders of magnitude. Similarly, the high-linearity TDC with a united-reference fractional counter for LiDAR applications ^[4] offers 19.5 ps resolution but only 999kS/s conversion rate, again far below the necessary sampling rate. These comparisons demonstrate that existing TDCs cannot simultaneously achieve the resolution and conversion rate demanded by IR-PWM-based systems.

However, achieving high linearity in the sub-gate delay region is challenging due to process, voltage, and temperature (PVT) variations. To mitigate these issues, prior state-of-the-art TDCs have relied on complex background calibration techniques, such as Data-Weighted Averaging (DWA) ^[5], Digital Calibration ^[6], or Look-Up Tables (LUT) ^[7]. While effective, these methods incur significant area and power overheads and increase design complexity. Conversely designs without linearization often suffer from poor differential nonlinearity (DNL), leading to missing codes ^[8].

In this paper we propose a calibration-free, high-linearity Vernier TDC optimized through a rigorous analytical methodology. To improve intrinsic linearity, a cascaded buffer structure is employed for the unit delay cells which statistically reduces the coefficient of variation (CV) of the delay by averaging random mismatches. Furthermore, a device-level sizing strategy is adopted where transistor channel lengths are tuned slightly larger than the minimum process size to balance high resolution with slew rate (jitter minimization), while channel widths are optimized at the ‘delay saturation point’ to maximize power efficiency and yield (targeting 5.2 sigma). Finally, to overcome the resolution limits of external instrumentation, an on-chip PWM generator with fine analog control is integrated, enabling precise characterization of the sub-picosecond resolution TDC. This multi-faceted optimization enables the proposed TDC to achieve an 8bit dynamic range with sub 3ps resolution and DNL<0.55 LSB without requiring any auxiliary calibration circuits. The rest of this paper is organized as follows: Section II describes the proposed architecture; Section III presents simulation and measurement results; and Section IV concludes the paper.

II. PROPOSED ARCHITECTURE

1. Time-to-Digital-Converter

The proposed TDC employs the Vernier architecture with 255 delay stages, each consisting of a slow buffer, a fast buffer, and an arbiter, as shown in Fig. 2. The number of stages was chosen to match the dynamic range of the IR-PWM transmitter, which requires 8-bit resolution ^[1]. Unlike conventional TDCs that use D flip-flops, the proposed design adopts an arbiter-based structure to minimize timing offsets and improve decision reliability ^[9]. In the Vernier scheme, the timing resolution is defined by the delay difference between the slow and fast paths. The slow-path buffer delay is designed to remain greater than that of the fast-path buffer even under the 5-$\sigma$ case, ensuring monotonicity and achieving a resolution of 2.94 ps. The 5-$\sigma$ design margin was selected to secure a 95% yield.

Fig. 2. (a) Block diagram of the TDC. (b) Unit stage of TDC. (c) Time diagram of TDC operation.

Fig. 3. Simulated propagation delay versus transistor width, illustrating the delay saturation effect.

To achieve high linearity without relying on complex calibration circuits, we optimized the unit delay cell analytically. First, a cascaded buffer structure was adopted instead of a single inverter. This reduces the coefficient of variation (CV) of the delay by approximately 29.5% due to the averaging effect of random mismatches.

Second, the transistor sizing was optimized to balance resolution, jitter, and conversion speed. The channel lengths were tuned to be slightly larger than the minimum process feature size. This strategy ensures a precise delay offset for high resolution while maintaining sharp transition edges (high slew rate) to minimize jitter. Unlike conventional designs that utilize significantly longer channels for delay extension, our approach prevents excessive degradation of the total conversion latency, thereby maintaining a high system throughput.

Furthermore, the transistor widths were selected at the ‘delay saturation point’ where the delay reduction diminishes due to the self-loading effect, as shown in Fig. 3. This optimization maximizes power efficiency while satisfying a 5.2 sigma yield target to prevent missing codes.

As shown in Fig. 2 the rising and falling edges of the PWM signal are fed into dedicated edge detectors, which then serve as the inputs to the arbiter. Within each stage, the signals propagate through the fast and slow delay lines and gradually converge. When the lagging falling edge catches up with the leading rising edge, the arbiter outputs logic high. All subsequent stages then produce a thermal code composed of logic high values, from which the input pulse width is derived.

Additionally, since the rising edge is applied to the slow path and the falling edge to the fast path, a delay mismatch can occur at the arbiter inputs. To mitigate this, fan-out adjustment was implemented at both input terminals to ensure delay matching. The arbiter is also equipped with a reset function, enabling re-initialization after each conversion cycle.

2. PWM generator for testing

To evaluate the resolution and accuracy of the TDC, a pulse train with a precisely tuned pulse width is required. For this purpose, we designed an on-chip PWM generator to produce the required test pulses, as shown in Fig. 4. The PWM generator incorporates a voltage-controlled ring oscillator operating in the frequency range of 1.2 GHz to 2.5 GHz, corresponding to a supply voltage (VDDL) range of 0.7 V to 1.2 V.

Fig. 4. (a) Block diagram of the proposed system. (b) Time diagram.

Instead of using the raw oscillator output, a frequency divider is utilized to generate a signal with a guaranteed 50% duty cycle. Subsequently a logic controller selects only the first pulse to generate a single-shot PWM waveform for the TDC input. Since direct measurement of the picosecond-scale pulse width is challenging due to the bandwidth limitations of I/O pads, the oscillator output is divided by a factor of 1024 to accurately calculate the generated pulse width.

The integration of this on-chip PWM generator was a metrological necessity because standard external equipment lacks the sub-picosecond resolution required to characterize the proposed TDC (1 LSB, 3ps). The on-chip generator allows for continuous fine-tuning of the pulse width via analog control voltage, enabling precise DNL/INL characterization without the signal distortion caused by external cabling and pad parasitics.

III. SIMULATION AND MEASUREMENT RESULTS

The proposed TDC is implemented using a 28-nm CMOS process. The complete chip micrograph is shown in Fig. 5, and the layout of a single TDC stage is depicted in Fig. 6. The TDC consists of 255 identical stages replicated horizontally. The actual area of the TDC was measured to be 5792 $\mu\text{m}^2$, while the PWM generator logic occupied 90.1 $\mu\text{m}^2$ as illustrated in Fig. 5.

Fig. 5. Die micrograph.

Fig. 6. Layout of a single TDC stage.

Fig. 7. CV Comparison of TDC Delay Difference Using Buffer or Inverter.

Fig. 7 presents the results of Monte Carlo simulations comparing buffer resolution and inverter resolution. The coefficient of variation (CV) of the buffer delay is 0.234, while that of the inverter delay is 0.332, representing a 29.5% reduction for the buffer. The CV is defined as follows:

where $\mu$ and $\sigma$ are mean and standard deviation.

The resolution of the TDC in the post layout simulation results, which is defined as the delay difference between the slow and fast buffers, are shown in Fig. 7. The TDC achieved a resolution of 3.17 ps under the TT corner condition at a supply voltage of 1.0 V. As the supply voltage increased, the delays in both the fast and slow paths decreased, which resulted in a lower resolution. Across the supply range of 0.9 V to 1.2 V and various corner conditions, the overall TDC resolution was found to be in the range of 2 ps to 5 ps, as illustrated in the simulation results in Fig. 8. The measured TDC resolution was 2.94 ps, which is within the simulated resolution range of 2.37 ps to 3.92 ps. The measured value reflects approximately an 8% deviation from simulation due to PVT variations, yet remains within the valid range.

Fig. 8. Resolution under varying supply voltage.

To verify the linearity of the TDC, Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) were measured. The measured DNL and INL values were less than $\pm0.55\text{ LSB}$ and $\pm1.5\text{ LSB}$, respectively, as plotted in Fig. 9, which confirms that the TDC exhibits monotonicity and good linearity. The linearity measurements were performed for codes 120–255 due to the maximum frequency limitation (2.5 GHz) of the on-chip test VCO. However, since the TDC consists of 255 physically identical delay stages replicated in the layout, the linearity performance verified in the upper range is statistically guaranteed for the entire dynamic range.

Fig. 9. Measured (a) DNL and (b) INL.

The maximum conversion rate is determined by the summation of the maximum propagation delay through the full delay line (4.5 ns) and the reset time (1.5 ns). This results in a throughput of 166 MS/s, which provides a sufficient margin over the system requirement of 10 MS/s. Continuous operation was functionally verified using a time-stretching readout technique, as shown in the measured waveforms in Fig. 10.

Fig. 10. Measured waveforms verifying continuous operation using time-stretching readout.

IV. CONCLUSIONS

This paper presents a TDC designed to measure the pulse width of a pulse train. The TDC was implemented in a 28-nm CMOS process and consists of a chain of 255 delay cells. A PWM generator was designed and implemented to generate a test signal with sub nanosecond pulse widths, utilizing a voltage-controlled ring oscillator. Measurement results demonstrate a time resolution of 2.94 ps, with the DNL and INL measured within $\pm0.55\text{ LSB}$ and $\pm1.5\text{ LSB}$, respectively.