I. INTRODUCTION

While artificial intelligence applications require high data bandwidth, low power consumption remains the most important design consideration for mobile memory interfaces. Thus, recent low-power double-data-rate (LPDDR) memory interfaces have scaled down the supply voltage (V_DDQ) of the output driver to improve energy efficiency ^[1]. However, the reduced V_DDQ degrades the signal-to-noise ratio (SNR), increasing susceptibility to inter-symbol interference (ISI). Although a decision-feedback equalizer (DFE) has been employed in LPDDR5X to reduce post-cursor ISI, the reduced supply voltage and signal swing exacerbate feedback timing constraints, limiting the maximum data rate of the voltage-domain receivers (RX).

A time-domain (TD) RX for V_SS-terminated signaling extends the upper limit of the feedback loop delay to more than one UI, thereby increasing the maximum data rate ^[2]. However, V_SS-terminated signaling is susceptible to simultaneous switching output noise (SSN) and has limited pre-emphasis applicability.

To address these issues, this letter presents two contributions. First, we validate the suitability of V_TT-terminated signaling with relaxed impedance matching (RIM) by comparing its power, equalization, and SSN with those of V_SS-terminated signaling. Second, we use a track-and-hold (T&H) circuit to prevent voltage-to-time converter (VTC) gain reduction from data transitions.

II. PROPOSED TD RX FOR V_TT-TERMINATED SIGNALING WITH RIM

1. Receiver Top Architecture

Fig. 1(a) presents the top architecture of the proposed RX, featuring a V_TT terminator, four VTCs, four 1-tap TD-DFEs, and a clock path for quarter-rate operation. Fig. 1(b) details the VTC, which integrates a T&H circuit with N- and P-type dynamic amplifiers. The T&H circuit holds the input signal during the decision phase. The held voltage is input to the dynamic amplifiers, which convert the voltage level into a time difference. Additionally, an offset calibration circuit corrects time offsets by adjusting the inverter pull-up/down strengths. Finally, a transition-direction aligner ensures uniform output transition directions for the subsequent TD-DFE.

Fig. 1. (a) RX top block diagram, (b) schematic of VTC with T&H circuit, and (c) 1-tap TD-DFE operation.

Fig. 1(c) shows the 1-tap TD-DFE operation. To cancel post-cursor ISI, the phase detector output of the previous bit adjusts the time difference between T_DFE,H and T_DFE,L using a 3-bit digitally controlled delay line (DCDL) with parallel binary-weighted segments. The DCDL provides the time difference of 0-7.3 ps, effectively enlarging the time difference reduced by ISI. The phase detector generates an RZ output based on the phase relationship between T_DFE,H and T_DFE,L, which is then restored to an NRZ signal via an SR latch.

2. Comparison of V_SS- and V_TT-Terminated Signaling

Fig. 2(a) shows that V_TT-terminated signaling with RIM (TX R_ON = 150 $\Omega$ and R_TERM = 50 $\Omega$) matches the signal swing and power of LPDDR5/5X with negligible signal integrity penalty in linear and low-reflective LPDDR channels ^[3]. Unlike V_SS-terminated signaling, V_TT-terminated signaling enables pre-emphasis, thereby enhancing SNR ^[4]. To compare SSN, which arises from data-dependent signaling current change ($ \Delta I $) through the power distribution network, we analyzed the $ \Delta I $ distribution on a 1-byte DQ bus using MATLAB by applying a one-million random data pattern. Fig. 2(b) shows the improved SSN for V_TT-terminated signaling with RIM.

Fig. 2. Comparison between V_SS-terminated LPDDR5/5X signaling and V_TT-terminated signaling with RIM: (a) output driver operation, signal swing, and signaling power, and (b) distributions of signaling current change ($ \Delta I $) for SSN analysis.

3. Time-Gap Enhancement with T&H Circuit

The time difference between T_VTC,H and T_VTC,L should be maximized to improve the bit error rate (BER). While the VTC delay is fixed at stable inputs, data transitions induce delay variations that reduce the time difference. A T&H circuit is employed to mitigate this issue. Under a 250-mV swing, the T&H circuit samples RX_IN at its peak to provide a stable VTC input. Consequently, the time gap extends from 6.1 ps to 16.6 ps, as shown in Fig. 3(b).

Fig. 3. Post-layout simulation results of time-gap enhancement with the T&H circuit.

III. MEASUREMENT RESULTS

The proposed RX was implemented in a 65-nm CMOS process. As shown in Fig. 4, the data path occupies a total area of 5820 $\mu$m², with an active area of 1948 $\mu$m². The RX operates at a 0.9-V V_DD and a 0.45-V V_TT. A PRBS-7 data signal with a 250-mV swing was applied to the test board through a channel ISI board using an arbitrary waveform generator. The BER was measured using an error detector.

Fig. 4. Die micrograph and area breakdown.

Fig. 5(a) shows the measured channel insertion loss, confirming a linear and low-reflective characteristic with a smooth roll-off. Fig. 5(b) shows the measured bathtub curves at a data rate of 14 Gb/s. Without TD-DFE, the eye was closed. However, by enabling the TD-DFE with a DCDL code 3'b110, the RX achieved a timing margin of 0.19 UI under the 13.45-inch channel for a BER lower than 10^-12. Fig. 5(c) shows the power breakdown. The RX data path consumes only 1.61 mW at 14 Gb/s.

Fig. 5. (a) Measured channel insertion loss (S₂₁), (b) measured bathtub curves, and (c) power breakdown.

Table 1 summarizes the performance comparison with recent RXs for memory interfaces. By employing a T&H circuit to enhance VTC gain, the proposed design maintains competitive data rates while achieving high energy efficiency.

IV. CONCLUSIONS

This letter presents a single-ended TD RX for low-power memory interfaces. Designed for V_TT-terminated signaling with RIM, the RX achieves a data rate of 14 Gb/s and an energy efficiency of 0.115 pJ/bit. This can be further improved by leveraging the pre-emphasis feed-forward equalizer at the transmitter, an advantage of V_TT-terminated signaling.