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  1. (Samsung Electronics, Co. 114, Samsung-ro, Pyeongtaek-si, Gyeonggi-do, Republic of Korea.)
  2. (Hankyong National University, 327, Jungang-ro, Anseong-si, Gyeonggi-do, Republic of Korea.)



Low pressure chemical vapor deposition (LPCVD), polycrystalline silicon (Poly-Si) process, furnace-vertical type LPCVD system, particle

I. INTRODUCTION

In mass production fabs for semiconductor manufacturing, efforts were made to improve yield and equipment utilization in order to reduce the cost per chip in advanced integration technologies. As integration density increased, the channel length of transistors decreased, which in turn led to a decline in both yield and equipment utilization [1, 2]. Among the various factors contributing to yield loss, particle contamination accounted for a significant portion [3, 4]. This was primarily due to the scaling down of design rules, where even small particles could cause critical defects in patterns, such as short-channel effects (SCE), drain-induced barrier lowering (DIBL), and gate-induced drain leakage (GIDL). When particles were generated during processing, the equipment had to be stopped and cleaned, resulting in a 20-30% reduction in utilization. This loss was more severe than that caused by equipment failure or scheduled maintenance.

Therefore, in very-large-scale integration (VLSI) mass production lines, it was essential to identify the root causes of particle generation and to develop particle-free process technologies to ensure high yield and maximize equipment utilization [1- 5]. In the semiconductor manufacturing process, one widely adopted method for forming ultra-thin films on wafers was the low-pressure chemical vapor deposition (LPCVD) process. This technique involved injecting reactive gases into the processing chamber, where thin films were formed through chemical reactions on the wafer surface. LPCVD represented one of several chemical vapor deposition (CVD) methods and was first introduced in the late 1970s. Despite its widespread use, research on particle generation within furnace-type LPCVD equipment remained limited. Although many semiconductor engineers expressed concern over particles generated during the LPCVD process, systematic investigations were hindered by a lack of standardized evaluation parameters at the laboratory level and insufficient time allocated for research in mass production fab. As a result, the understanding of particle behavior and its impact on yield and equipment performance was relatively underdeveloped.

In many cases, particles inside furnace-type LPCVD equipment can be removed during chamber cleaning, suggesting that the main cause of particle generation is due to particles deposited on internal chamber components because of the evaporation step deposition in the deposition process. This process recently forms polysilicon thin films, Si3N4 thin films, SiO2 thin films, etc. through chemical reactions up to 200 wafers at the same time. However, it is difficult to match the chemical composition of each wafer. As a result, wafers and unreacted gas particles react with some components in the equipment. The deposited films are primarily caused by molecular bonding forces to adhere to the inner chamber walls. It appears that when the external force is greater than the particle adhesion strength, it separates and floats inside the equipment, moves to the wafer surface, and adheres. Several researchers have studied the impact of external factors in a vacuum on particle recirculation. It is only empirically known that particles exist at specific points during the LPCVD process, and the appearance of particles during wafer transfer can be reduced by changing the pressure, gas ratio, and heat transfer process as the wafer moves through the process chamber [10, 11]. However, when discussing particle generation in a process-by-process, the mechanism of the effect of temperature changes has not been discussed in detail.

This study investigates the heat transfer mechanism within the reactor, focusing on the influence of quartz components in a furnace-vertical type low-pressure chemical vapor deposition (LPCVD) system [12]. The objective is to propose a strategy for controlling various defects that occur during the thin-film deposition process [13, 14]. Particle characteristics, composition, and morphology after polycrystalline silicon (Poly-Si) deposition under different process conditions are analyzed using energy dispersive X-ray spectroscopy (EDX) and vertical scanning electron microscopy (VSEM). Defects such as film peeling and cracking are identified. The study also examines wafer bending caused by internal stress resulting from non-uniform heat transfer in the reactor, which is recognized as a major contributor to particle generation and film defects. Experimental results confirm that suppressing wafer bending during the Poly-Si process effectively prevents wafer contamination. Based on these findings, the study suggests directions for process improvement. The proposed method is applied to the Poly-Si process in a mass production furnace-type LPCVD system to verify its scalability and manufacturability.

II. EXPERIMENTAL METHODS

The 12-inch wafer mass production device used in this study is a furnace type semiconductor manufacturing device, and the internal configuration of the device consists of a coil heater, an outer tube, an inner tube, and a boat. A total of 1 to 5 sections are divided into the temperature zones of thermocouple (TC) to check and adjust the process temperature for oxidation and deposition, and the tubes and boats that make up the furnace inner chamber is generally made of quartz materials that can be used in the high temperature zones, but SiC materials that can withstand higher temperature bands are used as needed. The device performing the LPCVD process additionally consists of a pump and necessary pipes, pressure gauges, and various valves to control the pressure [14- 17]. In order to check the defect factors inside the furnace type device, the temperature change analysis using TC wafer and the vibration inside the device using the auto vibration system (AVS) were checked, and the number, distribution, components, and model of particles generated in the poly-Si deposition process were checked using VSEM, EDX, and laser scattering inspection devices to analyze the data by measuring the effect of reducing particles through temperature control of each process.

The procedure of the experiments is as follows:

1. Particle generation type and component analysis at the location of the boat where the wafer is placed in the furnace type semiconductor manufacturing device (separated by zone).

2. Use A grade bare wafer to check the damage and vibration through scratch on the back side in the position of the boat where the wafer is located in the area where the part where the particle is clearly generated.

3. The associated temperature between the temperature profile and the warpage according to the facility design according to the reference paper [10, 20] is verified using TC wafers.

4. Using the information collected from the TC wafer, the evaluation is conducted by selecting the factors that can control the warpage in the wafer.

5. After initial preventive management (PM) of the facility, the optimal deposition of Poly-Si is found and reflected through experiments and applied to more than 10,000 wafers of mass production to observe the occurrence of particles.

III. ANALYSIS

When the types of particles generated in the Poly-Si deposition process were investigated, it was confirmed through EDX measurement that the particle generation map generated during the Poly-Si film deposition process had a gathering tendency at three locations on the wafer edge, as shown by the red spots in Fig. 1(a). The image of the generated particles was observed through SEM measurement, as shown in Fig. 1(b). It was confirmed that particles were concentrated on a specific corner and that a seed was generated on the wafer before deposition and then deposited along with Poly-Si. In Fig. 2, the top of the boat was relatively higher than the bottom in the Poly-Si deposition process. It was possible to indirectly confirm the influence of the generated particles on the vulnerability to gate induced drain leakage (GIDL), which causes problems in the operation of the final device [8, 17- 19].

Fig. 1. Particles generated during the Poly-Si thin film deposition process.

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Fig. 2. Comparison of process defects caused by GIDL generated by particles in the Poly-Si process.

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1. Study on the Types of Particle Generation in Poly-Si film in LPCVD furnace chamber

In the process, it was confirmed that the number of particles generated varies depending on the upper and lower positions of the boat where the wafer is mounted and transferred to the heater. Through this, the composition of the deposited film was inspected to confirm the identity of the deposited film on the boat and the wafer, and 25 particles generated in the mass production process were divided into 5 sections, and the occurrence rate was confirmed by classifying them into P1 to P5 sections in order from the top to the bottom of the boat. As a result, it was found that the occurrence rate was relatively higher in the P1 and P5 sections than in the middle sections of P2 and P3, and it was confirmed that there was a particularly high occurrence in the P1 section through Fig. 3.

Fig. 3. Longitudinal cross-sectional view of the furnace with heaters, coolers, and inner thermocouples [21] and particle emission rates by zone of the boat during long-term mass production.

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In Fig. 4, (a) is an SEM image with a Si film deposited on the boat in the P1 area, and (b) is an SEM image with a Si film deposited on the boat in the P4 area. It was confirmed that the particle source was more relatively distributed in the image of the P1 area. When analyzing the composition of the components shown in the (c) image, it was confirmed that most of them were Si components.

Fig. 4. The results of the component analysis of (a) boat top region, (b) boat bottom region, and (c) compound peak counts.

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From the review of previous studies, it was confirmed that the average temperature of the wafers located near 0 and 1, which are the top parts of the boat, were about 30 to 40 K lower than the average temperature of the wafers located in the center. This is due to the structure of the equipment, where the gas inlet at the bottom and the outlet at the top are close to the quartz tube area where the linear temperature distribution is exposed [4]. In the previous study, it was confirmed that the temperature difference in the temperature profile graph showed a similar number of particle defects from zone P1 to P5. As a result, it was confirmed that the particle generation was the highest in P1, which is the relatively coldest region, and the number of particles increased in the P5 region. This indicates that wafer warpage accelerates particle induction. To prove this, the vibration of the top and bottom parts of the boat was checked using AVS, and the vibration results are shown in Fig. 5. The red color represents the vibration result of the top region, and the blue color represents the vibration result of the bottom region. As expected, the vibration of the top region was measured to be 1.045G and the vibration of the bottom region was measured to be 1.028G, confirming that the vibration of the top part is greater. It was confirmed that when a temperature difference occurs between the upper and lower parts of the boat, the heater power increases to compensate for the temperature, which increases the temperature difference between the middle and outer parts of the wafer, thereby worsening the wafer warpage phenomenon.

Fig. 5. Red color is top region, and blue color is bottom region for boat by accelerated vibration service (AVS).

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At each boat position, scratches on the backside of the wafers were measured (using a 3-rod type boat) to check their lengths. The increase in friction on the backside of the wafers was compared by taking SEM images. In addition, wafer vibrations were measured using an AVS at a speed of 1000 mm/min. The level of scratch occurrence was 1.79 μm in the top area and 1.39 μm in the bottom area, and it can be seen in Fig. 6 that the top area has a greater degree of wafer damage.

Fig. 6. Comparison of wafer scratch depth (μm) between the top and bottom region of the boat.

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We conducted experiments under the conditions of Table 1 to find the conditions that alleviate the occurrence of wafer warpage. To evaluate the conditions for changing the stabilization time before starting the process, we placed thermocouple wafers at the top, center, and bottom of the boat, adjusted the boat speed, and reflected wait times of 0 min, 30 min, and 50 min from the reference value state, respectively. We adjusted the boat speed to 1000 mm/min (120 s required @open to close position) and 100 mm/min (960 s required @open to close position) and reflected the temperature ramp difference conditions (0 °C and 100 °C difference @ after boat load completion and low-pressure pumping start time). At this time, as shown in Fig. 7, when a certain stability was given, the top and bottom parts showed the most stable values compared to the before index.

Table 1. Experimental conditions to mitigate wafer warpage.

Items Unit Value
Temperature gap (Process - standby) °C 0, 100
Wait time min 0, 30, 50
S.Pump step N2 flow slm 0, 10, 20
Boat speed mm/min 100, 1000

Fig. 7. Evaluation of back side (B/S) scratch depth (μm) verification results by evaluation conditions.

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Based on the above results, the wait time (Process - Standby, °C) was subdivided into 5-minute intervals from 0 minutes to 50 minutes, and the particle evaluation of the top and bottom parts was performed. The results were confirmed. In the S.Pump Step (the step where pumping down starts at low pressure after the standby step), the N2 flow rate was evaluated in the order of 0 slm, 2, 4, 8, 9, 10, and 20 slm, and the particle results were confirmed. As shown in Fig. 8, the particle increase with wait time showed a change in stability after a stabilization time of about 15 minutes, where the particle map concentrated at the rad part of the boat of the wafer shown in red, as shown in the particle map of the wafer indicated in blue, disappeared. Additionally, in the experiment reflecting the change in N2 flow rate to control convective heat transfer, it was confirmed that the point at which the top (T) and bottom (B) parts commonly stabilize is from about 4 slm or more when checking the particle map of the wafer. Prior to subsequent evaluation using the T/C wafer, particle evaluation was performed using NPW. Results showed that at a boat speed of 100 mm/min, a N2 concentration of 10 slm did not significantly differ from 20 slm in the upper region, but slightly better results (average 0.74) were observed in the lower region. This suggests that excessive N2 concentration may be the cause of the supercooling problem [22, 23].

Fig. 8. The result of the change in the number of particles with changes in waiting time at the top and bottom of the boat.

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As shown in Fig. 9(a), a T/C wafer with 17 points that can be read in-wafer was placed in the boat slots of top (T), center (C), and bottom (B) to evaluate the temperature difference between the center point and edge point of the wafer to minimize wafer warpage. From the above results, when the wait time was 0 min, T showed an in-wafer temperature difference of 15.55 °C, C showed 13.72 °C, and B showed 12.8 °C. As shown in Fig. 9(b), when the wait time was 30 min, the particle-defective areas T and B decreased to 11.08 °C and 9.78 °C, respectively. Additionally, by adjusting the amount of N2 in the S.pump step, when the wait time was 20 min and 10 slm (N2 at S.pump step) was applied to the top area, which was the most particle-defective area, the most stable value of 10.42 °C was confirmed.

Fig. 9. (a) Before edge to center delta temperature for top, middle and bottom zone; (b) edge to center delta temperature for top (T), center (C), and bottom (B) zone by addition 30-min wait time; (c) comparison of edge-to-center delta temperature in the top zone before and after treatment (20-minute wait and N2 flow 10 slm).

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2. Study on the Types of Particle Generation in Poly-Si film in Boat of LPCVD furnace chamber

In the accumulated usage of more than 100,000 Å, the failure of the rod area in the slot of the boat where the wafer is directly placed was analyzed. The particle was examined in the poor top area, P1 zone, and the relatively good P3 zone. The inspection area was divided into 1-4 areas as shown in Fig. 10. The results showed that the peeling phenomenon of the film deposited in the P1 zone areas 1 and 3 was relatively severe. In Fig. 11, the hydrogen concentration of the Poly-Si film deposited on the Non-Pattern Wafer (NPW) at the top, middle, and bottom of the boat was confirmed using TOF-SIMS, but no significant level was found. Additionally, a NPW sample was prepared and an average of 1.75 μm of Poly-Si was deposited. The morphology was confirmed to be poor using a vertical scanning electron microscope (VSEM) as shown in Fig. 12. This is made of quartz material and cleaned before use. The boat is regularly replaced and generally performs a pre-deposition process without wafers for uniform deposition on the wafer. This is called the pre-depo process. Initially, it can cause wafer distortion during mass production due to unwanted morphology, which can increase the probability of particle generation due to frictional impact. To resolve this issue, a method to control the warpage of the wafer and increase the surface area of the boat to minimize the accumulated thickness of Poly-Si is proposed. This allows for particle-stable production.

Fig. 10. The result of the change in the number of particles with changes in waiting time at the P1 zone and P3 zone of the boat.

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Fig. 11. Hydrogen concentration at the wafer edge and center (CTR) region, top and bottom of the wafer boat using TOF-SIMS.

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Fig. 12. Morphology of NPW by vertical scanning electron microscope (VSEM).

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We secured a delta of 10.42 °C through experiments to reduce the temperature difference from the edge to the center of the wafer and added experiments to find favorable morphological conditions on the boat surface, which was confirmed to be less than 1.2 μm in previous studies [10]. Additionally, it was confirmed that the occurrence of cracks in the deposited film becomes more severe as the thickness increases, even with small stresses [11]. To address this, we used VSEM experiments to examine the morphological state of the boat rod and confirmed morphological stability when grown to 0.95 μm at 550 °C, as shown in Fig. 13. Furthermore, to reduce the total thickness of the film deposited on the boat during mass production, we modified the shape of the rod part of the boat to increase the surface area by creating a trench in the lower part of the boat rad, as shown in Fig. 14, resulting in an increase of approximately 12.9% in surface area. As shown in Fig. 15, by reflecting the conditions in Table 2 in the long-term mass production evaluation, we confirmed that the particle reduction effect was approximately 6.7% and verified that the mass production period could be extended by approximately 30%. This confirmed that by increasing the surface area and thus reducing the average thickness, favorable results for particles can be obtained.

Fig. 13. Morphology of wafer after Pre-Depo by VSEM.

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Fig. 14. Boat rod images: (a) reference and (b) surface area increase for 12.9%.

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Fig. 15. The improved item has been applied to the result particle counts: (a) boat slot and (b) product wafer.

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Table 2. Final apply conditions to mitigate wafer warpage.

Items (unit) ΔT (Process-standby) °C Wat time min N2 (S. step) slm Boat speed mm/min
Reference 100 5 0 1000
Apply 0 30 10 100

IV. CONCLUSION

In this study, during the LPCVD process in a batch-type structure equipment, the occurrence of particle defects during the poly-Si film deposition process was investigated. It was found that reducing the temperature difference between the center and edge of the wafer was crucial for preventing warpage. Furthermore, managing the vibration of the boat during its ascent and the condition of the film being deposited on the boat were crucial processes. A combination of complex factors is causing particle generation. This could be addressed by evaluating the internal gas flow to control internal convection and by considering the thermal stabilization time of the wafer. Additionally, even if a slight warpage of the wafer occurred, it was observed that the number of particle defects decreased as the film deposition thickness in the radial area of the boat, where the wafer is placed, decreased. Therefore, it was confirmed that designing a mechanism to increase the surface area of the boat could aid in stable mass production. Changing the boat model is a common practice in current semiconductor component manufacturing technology and is easy to manage. However, more importantly, it is important to vary the boat model to suit the characteristics of the deposition film.

ACKNOWLEDGMENTS

This study was supported by Samsung Electronics, Co. internal research and innovation initiative.

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Dae-man Seo
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Dae-man Seo received his bachelor's degree from the Department of Semiconductor Engineering at Samsung Institute of Technology in 2011 and his master's degree from Hanyang University in 2014. Since 2023, he has been a doctoral student in the Department of Electrical and Electronic Engineering at Hankyong National University. From 1996 to the present, he has worked as a senior researcher at Samsung Electronics Co., contributing to the mass production of semiconductor manufacturing equipment. He is currently conducting research on the mass production stabilization of epitaxial, ALD, and LPCVD manufacturing equipment.

Sung-man Lee
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Sung-man Lee received his bachelor's degree from Kyung-Hee Cyber University in 2019. He has been working at Samsung Electronics Co. since 2003, where he is responsible for field equipment operation, problem resolution, and standardization activities. In 2016, he conducted defect analysis through powder formation mechanism analysis in the TEOS process. Since 2023, he has been conducting research on stabilizing mass production of manufacturing equipment by analyzing the structure and input parameters of POLY and ALD manufacturing equipment.

Seung-jae Baik
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Seung-jae Baik received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 1994, 1996, and 2001, respectively. From 2001 to 2009, he was with Samsung Electronics Co., Yongin, South Korea, where he contributed to novel Si devices, high-density flash memory devices, and charge trap flash memory devices, as a Senior Engineer and a Principal Engineer. From 2009 to 2012, he was with KAIST as a Research Professor, where he contributed to thin film Si solar cells, quantum dot solar cells, new memory materials, and devices. From 2012 to 2022, he was with Hankyong National University, Anseong-si, South Korea, as an Associate Professor. Since 2023, he again has been with Samsung Electronics Co., Yongin, South Korea as a Master. His current research interests include NAND flash and nonvolatile memory device applications.

In-Ho Lee
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In-Ho Lee received the B.S., M.S., and Ph.D. degrees in electrical engineering from Hanyang University, Ansan, South Korea, in 2003, 2005, and 2008, respectively. He worked for LTE-Advanced standardization with Samsung Electronics Company, from 2008 to 2010. He was a Postdoctoral Fellow with the Department of Electrical Engineering, Hanyang University, from April 2010 to March 2011. Since March 2011, he has been a Professor with the School of Electronic and Electrical Engineering, Hankyong National University, Anseong-si, South Korea. From February 2017 to February 2018, he was a Visiting Associate Professor with the Department of Electrical and Computer Engineering, The University of British Columbia, Vancouver, Canada. His present research interests include non-orthogonal multiple access, millimeter wave wireless communications, cooperative communications, multi-hop relaying, transmission and reception of multiple-input and multiple-output communications, multicast communications, and deep-learning algorithms. He is a Senior Member of IEEE.