SCR-Based ESD Protection Device with an Added Metal Discharge Path for 5-V Applications
Dong-Hyeon Kim1
Jae-Yoon Oh1
Min-Seo Kim1
Cheon-Hoo Jeon1
Jung-Won Kang1
Yong-Seo Koo1,*
-
(Dept. Engineering of Foundry, Dankook University)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Avalanche breakdown, positive feedback, SCR (silicon controlled rectifier), LVTSCR (low voltage trigger SCR), holding voltage
I. INTRODUCTION
In the modern semiconductor industry, the rapid advancement of semiconductor process
technology has led to the miniaturization of various electronic devices. This technology,
known as high integration technology, enables the scaling down of key process parameters
such as gate oxide thickness, metal interconnect thickness, and junction depth in
semiconductor devices. Such technological progress has significantly contributed to
improving integration density and yield in semiconductor manufacturing processes.
However, as device scaling continues, the sensitivity to Electrostatic Discharge (ESD)
phenomena increases, leading to a higher failure rate in IC circuits. In fact, it
has been reported that more than 10% of IC failures are caused by ESD events, which
has driven extensive research on ESD protection circuits to prevent such damage [1]. Currently, the representative devices used for ESD protection include GGNMOS, SCR,
and LVTSCR. The common design objective of these devices is to remain inactive during
the normal operation of IC circuits and to respond rapidly only when an ESD event
occurs, thereby protecting the circuit [2-
4]. The Gate-Grounded NMOS (GGNMOS) is widely used as an ESD protection device due to
its excellent compatibility with standard CMOS processes. In the GGNMOS structure,
the gate terminal is connected to the cathode or source terminal. In other words,
instead of applying a voltage to the gate to control the channel region, the device
operates by activating the internal parasitic BJT within the NMOS to discharge the
ESD current. However, compared to the SCR, the GGNMOS exhibits lower current-driving
capability since only a single parasitic BJT is active. To overcome this limitation
and enhance its current-driving performance, the GGNMOS is typically designed with
a multi-finger structure [5-
7]. The Silicon Controlled Rectifier (SCR) is a device that discharges ESD-induced current
through the operation of internal parasitic BJTs. Unlike the GGNMOS, the SCR operates
using both parasitic PNP and NPN BJTs, which function in a positive feedback mechanism
where each BJT supplies current to the base region of the other. Through this operation,
the SCR exhibits a much higher current-driving capability than the GGNMOS when compared
on a single-device basis. Due to this characteristic, the SCR achieves greater robustness
under ESD stress, meaning it can sustain a higher It2 value. However, the SCR has a very high trigger voltage and an extremely low holding
voltage. These electrical characteristics can induce latch-up phenomena in IC circuits,
which undermines its fundamental purpose of circuit protection. Therefore, despite
its superior robustness, the SCR still requires improvement in terms of reliability
[8-
10]. The LVTSCR (Low-Voltage-Trigger SCR) is an ESD protection circuit designed through
structural modification to reduce the high trigger voltage of the conventional SCR.
In this structure, a heavily doped N+ region is inserted between the wells to induce avalanche breakdown at a lower voltage,
thereby enabling faster triggering. Through this approach, the LVTSCR effectively
improves the high trigger voltage characteristic of the conventional SCR. However,
it still suffers from a low holding voltage. To prevent interference with the normal
operating voltage range of IC circuits, a higher holding voltage is required for improved
reliability [11-
14].
II. PROPOSED ESD PROTECTION DEVICE
1. Operating Principle of the Proposed ESD Protection Device
Fig. 1 shows the cross-sectional structures of the SCR, LVTSCR, and the proposed ESD protection
device. The proposed device was designed to improve the low holding voltage of the
conventional LVTSCR. To verify this improvement, the operating principles of the conventional
SCR and LVTSCR were analyzed, and the operating mechanism and electrical characteristics
of the proposed ESD protection device were compared. The operating principle of the
SCR is as follows. When no ESD event occurs, the device remains inactive due to the
reverse bias between the wells. However, when an ESD surge is applied to the anode,
the potential of the N-well gradually increases. Once the N-well potential exceeds
the avalanche breakdown threshold, avalanche breakdown occurs, generating electron-hole
pairs (EHPs). The generated holes then move toward the P-well, raising its potential
and forward-biasing the junction between the P-well and the N+ cathode. As a result, the parasitic transistor QNPN1 inside the SCR is turned on,
discharging the ESD surge current through the parasitic BJT conduction path. Due to
this operating mechanism, the SCR exhibits a high trigger voltage, which must be reduced
for integration into IC circuits. In addition, although the internal parasitic BJTs
operate through a positive feedback mechanism that provides high current-driving capability,
this also results in an extremely low holding voltage. The LVTSCR was developed to
improve the high trigger voltage of the conventional SCR. In the LVTSCR structure,
a heavily doped N+ region is inserted between the wells. This design lowers the avalanche breakdown
voltage that occurs between the relatively lightly doped wells, as the breakdown voltage
decreases when the junction involves a more heavily doped implant region. In addition,
the LVTSCR incorporates a GGNMOS structure within the conventional SCR. As a result,
the effective base region of the parasitic NPN BJT beneath the gate area-where no
Shallow Trench Isolation (STI) is present-becomes shorter. Consequently, the parasitic
NPN BJT turns on more quickly, allowing the LVTSCR to achieve a lower trigger voltage.
As a result, the LVTSCR retains the fundamental operating principle of the conventional
SCR while incorporating a structural advantage that lowers the trigger voltage through
avalanche breakdown occurring between the N+ region and the P-well. However, both the SCR and LVTSCR require a higher holding
voltage for practical application in IC circuits. The proposed ESD protection device,
similar to the LVTSCR, incorporates a heavily doped P+ region between the wells to lower the trigger voltage and introduces an additional
metal path to form a new discharge path for the parasitic NPN BJT. As a result, the
proposed structure achieves a higher holding voltage compared to the conventional
SCR and LVTSCR. Furthermore, by adding a Deep N-well, the proposed device enables
the parasitic NPN BJT to operate more widely in the lower region, thereby achieving
higher current-driving capability. The operating principle of the proposed ESD protection
device is as follows. When no ESD event occurs, the device remains inactive due to
the reverse bias between the N-well and P+ region. However, when an ESD surge is applied to the anode, the potential of the
N-well continuously increases. Once the N-well potential exceeds the avalanche breakdown
threshold with the P+ region, avalanche breakdown occurs, generating electron-hole pairs (EHPs). The generated
holes then move toward the P-well and metal regions, which reduces the current flowing
into the P-well. As a result, the gain of the positive feedback loop formed along
the BJT discharge path decreases, leading to an increase in the holding voltage. The
holes continue to flow into the P-well, further raising its potential, and consequently,
the P-well and N+ cathode become forward-biased. At this point, the parasitic BJTs QNPN1 and QNPN2
are activated, discharging the ESD surge current through the parasitic BJT conduction
paths.
Fig. 1. Cross-sectional structures of (a) SCR, (b) LVTSCR, and (c) the proposed ESD
protection device.
2. Analysis of TCAD Simulation Results
In this study, TCAD simulations were performed using Synopsys TSUPREM-4 and MEDICI
to verify the operating principle of the proposed ESD protection device. Fig. 2 shows the cross-sectional structures of the SCR, LVTSCR, and the proposed ESD protection
device implemented through TCAD simulations. During the electrical characteristic
calculations, the mesh density was gradually increased in the vicinity of the junction
regions to enable more accurate numerical analysis. The width of each ESD protection
device was fixed at 1 $\mu$m, while the lengths were set to 13 $\mu$m for the SCR-based
ESD protection device, 13 $\mu$m for the LVTSCR, and 17 $\mu$m for the proposed ESD
protection device. In addition, the lengths of the heavily doped N- and P-type implant regions were set to 1 $\mu$m, and the spacing between each implant
was fixed at 1 $\mu$m. For the ion implantation conditions, the heavily doped N- and
P-type implants were set to implantation doses of 3 $\times$ 1015 cm-2 or higher, while the NWELL and PWELL regions were set to implantation doses of 8
$\times$ 1012 cm-2 or higher. Each implantation condition was repeated four times for the simulations.
Fig. 2. Cross-sectional structures of (a) SCR, (b) LVTSCR, and (c) the proposed ESD
protection device implemented by TCAD simulation.
The impact ionization simulation results for each structure are shown in Fig. 3. In this impact ionization analysis, a gradually increasing input voltage was applied
to the anode terminal from 0.1 to 30 V with a voltage step of 0.1 V, while the cathode
terminal was grounded. As shown in Fig. 3(a), the avalanche breakdown of the SCR is observed to occur between the wells. In Fig. 3(b), a high level of impact ionization is generated at the N+ region and the P-well of the LVTSCR, indicating that the LVTSCR undergoes avalanche
breakdown at a lower voltage compared to the conventional SCR. Finally, for the proposed
ESD protection device shown in Fig. 3(c), a high level of impact ionization is observed at the N-well and P+ regions. Through this analysis, the avalanche breakdown locations of each device
were identified. Fig. 4 presents the total current flowline simulation results of the SCR, LVTSCR, and the
proposed ESD protection device. The simulations were performed under the same voltage
bias conditions used in the impact ionization analysis. As shown in the figure, the
discharge paths of the parasitic BJTs in each device can be identified. In particular,
for the proposed ESD protection device shown in Fig. 4(c), the current is observed to flow through an additionally formed metal path.
Fig. 3. Impact ionization regions of (a) SCR, (b) LVTSCR, and (c) the proposed ESD
protection device implemented by TCAD simulation.
Fig. 4. Total current flowline of (a) SCR, (b) LVTSCR, and (c) the proposed ESD protection
device implemented by TCAD simulation.
III. RESULTS AND DISCUSSION
1. Comparison and analysis
The SCR, LVTSCR, and proposed ESD protection devices designed in this study were fabricated
using a 0.18-$\mu$m BCD process and were identically designed with a width of 100
$\mu$m based on heavily doped implant conditions. The device areas of the SCR, LVTSCR,
and the proposed ESD protection device are 24 $\mu$m $\times$ 102 $\mu$m (2448 $\mu$m2), 26 $\mu$m $\times$ 102 $\mu$m (2652 $\mu$m2), and 35.84 $\mu$m $\times$ 109.6 $\mu$m (3928 $\mu$m2), respectively. Fig. 5 shows the layout of the proposed ESD protection device along with a magnified image
of the fabricated device. In addition, the electrical characteristics of the proposed
ESD protection device were analyzed using a Transmission Line Pulse (TLP) system.
Fig. 5. (a) Layout image of the proposed ESD protection device, and (b) magnified
image of the proposed device fabricated using the 0.18-$\mu$m process.
Fig. 6. Simplified layout of the proposed ESD protection device.
Fig. 7 presents the TLP-measured I-V characteristic curves of the SCR, LVTSCR, and the proposed
ESD protection device. According to the TLP measurement results, the trigger voltages
of the SCR, LVTSCR, and the proposed ESD protection device were measured to be 20
V, 14.22 V, and 14.47 V, respectively. Compared with the conventional SCR, the proposed
device exhibits a trigger voltage reduced by more than 6 V and shows a trigger voltage
comparable to that of the LVTSCR. This reduction in trigger voltage is attributed
to the fact that avalanche breakdown occurs at a lower voltage between the heavily
doped implant and the well regions. In addition, the holding voltages of the SCR,
LVTSCR, and the proposed ESD protection device were measured to be 3.27 V, 3.56 V,
and 6.11 V, respectively, indicating that the proposed device possesses electrical
characteristics suitable for IC circuits operating at a supply voltage of 5 V. The
increase in holding voltage of the proposed ESD protection device is attributed to
the dispersion of holes generated after avalanche breakdown, which are distributed
and transported through both the P-well and an additionally formed metal path. Unlike
the conventional SCR and LVTSCR, in which holes generated after avalanche breakdown
flow only through the P-well, the proposed device allows hole transport through the
additional metal path as well.
Fig. 7. TLP measurement results of the SCR, LVTSCR, and the proposed ESD protection
device.
As a result, the gain of the positive feedback loop formed along the parasitic BJT
discharge path is reduced, leading to an increase in the minimum operating voltage
of the parasitic BJT. Consequently, the proposed ESD protection device exhibits a
higher holding voltage compared to the conventional SCR and LVTSCR. However, due to
the reduced gain of the positive feedback loop along the parasitic BJT discharge path,
the current driving capability of the proposed ESD protection device is degraded,
resulting in an increase in the on-resistance (Ron). Consequently, compared with the
conventional SCR and LVTSCR, the proposed device exhibits a higher Ron value. Furthermore,
this increase in resistance leads to a reduction in the It2 value, which represents the point at which the ESD protection device undergoes thermal
failure.
Table 1. Summary of the electrical characteristics of the SCR, LVTSCR, and the proposed
ESD protection device.
|
Structure
|
Trigger voltage (Vt1) [V]
|
Holding voltage (Vh) [V]
|
2nd breakdown current (It2) [A]
|
On-state resistance (Ron) [$\Omega$]
|
|
SCR
|
20
|
3.27
|
> 9.5
|
0.81
|
|
LVTSCR
|
14.22
|
3.56
|
> 9.5
|
1.11
|
|
The proposed ESD protection device
|
14.47
|
6.11
|
8.0
|
1.83
|
2. Design for improving current driving capability
Fig. 8 shows the structure of the proposed ESD protection device in which a heavily doped
P+ region and a P-well were additionally inserted at the anode side to form an additional
parasitic PNP BJT path. This design approach enables more parasitic BJTs to operate
simultaneously compared to the previously proposed ESD protection device, thereby
enhancing the current driving capability. The operating principle of the device shown
in Fig. 8 is similar to that of the proposed ESD protection device; however, when an ESD event
occurs, the additional parasitic PNP BJT path is activated and participates in the
discharge operation.
Fig. 8. Cross-sectional structure of the proposed ESD protection device with an added
PNP BJT.
3. Comparison and analysis
Fig. 9. Simplified layout of the proposed ESD protection device with an added PNP
BJT.
Fig. 10 shows the TLP-measured I-V characteristic curves of the proposed ESD protection device
and the proposed device with an additional PNP BJT. This improvement is attributed
to the enhanced current driving capability resulting from the operation of the additionally
formed PNP BJT at the anode side. Analysis of the TLP measurement results indicates
that the Ron value is reduced, and consequently, the thermal robustness of the device
is improved, leading to an increase in the It2 value. Although this design approach is effective in enhancing the current driving
capability, it suffers from the drawback of increased device area due to the addition
of the parasitic BJT discharge path. The area of the previously proposed ESD protection
device is 35.84 $\mu$m $\times$ 109.6 $\mu$m, corresponding to 3928 $\mu$m2, whereas the area of the ESD protection device increases to 42.73 $\mu$m $\times$
109.6 $\mu$m, corresponding to 4683 $\mu$m2, when the PNP BJT is additionally formed.
Fig. 10. TLP measurement results of the proposed ESD protection device and the proposed
ESD protection device with an added PNP BJT.
Table 2. Electrical characteristics of the proposed ESD protection device with an
added PNP BJT.
|
Structure
|
Vt1 [V]
|
Vh [V]
|
It2 [A]
|
Ron [$\Omega$]
|
|
The proposed ESD protection device
|
14.22
|
6.11
|
8.0
|
1.83
|
|
The proposed ESD protection device with an added PNP BJT
|
14.42
|
5.75
|
> 9.5
|
1.25
|
4. Analysis of Electrical Characteristics According to Design Parameter D1
Fig. 11 shows the structure of the proposed ESD protection device with an added highly doped
N+ floating region. The floating region extends the effective base region of the parasitic
PNP BJT, and the presence of the highly doped N+ region in the discharge path slows down the carrier recombination rate within the
base region of the parasitic PNP BJT. As a result of this design, the current gain
($\beta$) and loop gain of the parasitic PNP BJT decrease, leading to an increase
in the operating voltage of the parasitic PNP BJT. Therefore, this structural design
contributes to an improvement in the holding voltage of the device. Fig. 11 shows the TLP measurement results according to variations in the length of the N+ floating region, defined as design parameter D1. The lengths of D1 were set to 3
$\mu$m, 5 $\mu$m, and 7 $\mu$m, increasing by 2 $\mu$m for each case. The TLP results
indicate that as D1 increased by 2 $\mu$m, the holding voltages were measured to be
7.3 V, 8.22 V, and 9.7 V, respectively. This result can be attributed to the reduction
in current gain ($\beta$) and loop gain of the parasitic PNP BJT, as previously discussed,
which leads to an increase in holding voltage. Therefore, it was confirmed that introducing
and extending the design parameter D1 serves as an effective design approach that
directly contributes to enhancing the holding voltage of the device.
Fig. 11. Cross-sectional structure of the proposed ESD protection device with the
added design parameter D1.
Fig. 12. TLP measurement results of the proposed ESD protection device and the proposed
ESD protection device with an added PNP BJT.
Table 3. Electrical characteristics of the proposed ESD protection device with an
added PNP BJT.
|
Design parameter [$\mu$m]
|
Vt1 [V]
|
Vh [V]
|
|
D1
|
1
|
14.22
|
6.11
|
|
3
|
14.59
|
7.3
|
|
5
|
14.72
|
8.22
|
|
7
|
14.54
|
9.7
|
IV. CONCLUSIONS
In this study, an ESD protection device with an improved holding voltage was proposed.
The proposed ESD protection device exhibits a higher holding voltage compared to the
conventional SCR and LVTSCR, while maintaining a trigger voltage comparable to that
of the LVTSCR. As a result, the proposed device was verified to be suitable for IC
circuits operating at a supply voltage of 5 V. However, the design approach of the
proposed ESD protection device reduces the gain of the positive feedback loop due
to the additionally formed metal discharge path, which degrades the current driving
capability and leads to an increase in the on-resistance (Ron). Consequently, the
thermal robustness of the device is reduced, resulting in a decrease in the It2 value. To address this issue, a design approach incorporating an additional PNP BJT
path was adopted, and the Ron value was confirmed to be effectively reduced compared
to that of the original device. Nevertheless, this design approach increases the device
area, and therefore, optimization of the electrical characteristics must be carefully
considered by taking the area overhead into account. Furthermore, the electrical characteristics
were investigated as a function of the design parameter D1, and an effective modulation
of the holding voltage was confirmed. The proposed ESD protection device targets IC
circuits operating at a 5 V supply voltage, and based on the electrical characteristics
verified in this study, it is expected that the proposed device can provide effective
ESD protection with high reliability when applied to practical IC circuits.
ACKNOWLEDGMENTS
This study was conducted with the support of the Compound Material-based Next Generation
Power Semiconductor Technology Development Project of the Ministry of Trade, Industry
and Energy and the Korea Institute for Industrial Technology Evaluation (RS-2022-00143842,
?Single/Three-phase AC/DC Converter Smart Power IC using SiC MOSFET devices?) and
This study was supported by the Technology Innovation Program (or Industrial Strategic
Technology Development Program) ("RS-2023-00235759", Development of Wireless Charging
SoC with Built-In ESD Protection Circuit for Wearable Devices) funded By the Ministry
of Trade, Industry & Energy(MOTIE, Korea) (2410009645) and This study was supported
by National R&D Program through the National Research Foundation of Korea(NRF) funded
by Ministry of Science and ICT (RS-2021-NR057239)
REFERENCES
Amerasekera A. , Duvvury C. , Anderson W. , Gieser H. , Ramaswamy S. , 2002, ESD in
Silicon Integrated Circuits
Semenov O. , Sarbishaei H. , Sachdev M. , 2008, ESD Protection Device and Circuit
Design for Advanced CMOS Technologies
Ker M.-D. , Yen C.-C. , 2008, Investigation and design of on-chip power-rail ESD clamp
circuits without suffering latchup-like failure during system-level ESD test, IEEE
Journal of Solid-State Circuits, Vol. 43, No. 11, pp. 2533-2545
Ker M.-D. , 2006, ESD (electrostatic discharge) protection design for nanoelectronics
in CMOS technology, Advanced Signal Processing, Circuit and System Design Techniques
for Communications, pp. 217-279
Zhang P. , Wang Y. , Jia S. , Zhang X. , 2011, A novel multi-finger layout strategy
for GGnMOS ESD protection device, Proc. of the 9th IEEE International Conference on
ASIC, pp. 275-278
Ker M.-D. , Chen J.-H. , Hsu K.-C. , 2005, Self-substrate-triggered technique to enhance
turn-on uniformity of multi-finger ESD protection devices, Proc. of the IEEE VLSI-TSA
International Symposium on VLSI Technology, pp. 17-18
Do K.-I. , Song B.-B. , Koo Y.-S. , 2020, A gate-grounded NMOS-based dual-directional
ESD protection with high holding voltage for 12-V application, IEEE Transactions on
Device and Materials Reliability, Vol. 20, No. 4, pp. 716-722
Ker M.-D. , Hsu K.-C. , 2005, Overview of on-chip electrostatic discharge protection
design with SCR-based devices in CMOS integrated circuits, IEEE Transactions on Device
and Materials Reliability, Vol. 5, No. 2, pp. 235-249
Lin C.-Y. , Wu Y.-H. , Ker M.-D. , 2016, Low-leakage and low-trigger-voltage SCR device
for ESD protection in 28-nm high-k metal-gate CMOS process, IEEE Electron Device Letters,
Vol. 37, No. 11, pp. 1387-1390
Huang Y.-C. , Ker M.-D. , 2013, A latchup-immune and robust SCR device for ESD protection
in 0.25-$\mu$m 5-V CMOS process, IEEE Electron Device Letters, Vol. 34, No. 5, pp.
674-676
Do K.-I. , Koo Y.-S. , 2020, A new SCR structure with high holding voltage and low
on-resistance for 5-V applications, IEEE Transactions on Electron Devices, Vol. 67,
No. 3, pp. 1052-1058
Lou L. , Liou J. J. , 2007, An unassisted, low-trigger-, and high-holding-voltage
SCR (uSCR) for on-chip ESD-protection applications, IEEE Electron Device Letters,
Vol. 28, No. 12, pp. 1120-1122
Seo U. Y. , Lee J. M. , Kwon S. W. , Koo Y. S. , 2024, Design of high-reliability
LDO regulator incorporated with SCR-based ESD protection circuit using transient switch
structure, IEICE Electronics Express, Vol. 21
Ker M.-D. , Chang H.-H. , 1998, How to safely apply the LVTSCR for CMOS whole-chip
ESD protection without being accidentally triggered on, Proc. of the Electrical Overstress/Electrostatic
Discharge Symposium, pp. 72-85
Dong-Hyeon Kim was born in Seongnam, Republic of Korea, in 2000. He has been a master's
course in Foundry Engineering at Dankook University since 2024. His current research
interests include electrostatic discharge (ESD) protection circuit design and power
semiconductor devices such as BJT with a focus on ESD protection circuit design.
Jae-Yoon Oh was born in Seoul, Republic of Korea, in 1998. He has been a master's
course in Foundry Engineering at Dankook University since 2024. His current research
interests include electrostatic discharge (ESD) protection circuit design and power
semiconductor devices such as BJT with a focus on ESD protection circuit design.
Min-Seo Kim was born in Seoul, Republic of Korea, in 2000. She has been a master's
course in Foundry Engineering at Dankook University since 2024. Her current research
interests include electrostatic discharge (ESD) protection circuit design and power
semiconductor devices such as BJT with a focus on ESD protection circuit design.
Cheon-Hoo Jeon received the B.S. and Ph.D. degrees in electronic and electrical engineering
from the Pohang University of Science and Technology (POSTECH), Pohang, South Korea,
in 2014 and 2021, respectively. From 2021 to 2023, he was a Senior Engineer with Samsung
Electronics, Hwaseong, South Korea, where he worked on CMOS image sensor designs.
In 2023, he joined the Department of Convergence Semiconductor Engineering, Dankook
University, Yong-in, South Korea, where he is currently an Assistant Professor. His
research interests include low-power analog circuits including sensor interface circuits,
battery management systems and wireless sensor systems for biomedical devices.
Jung-Won Kang received the B.S. degree in electronic engineering from Korea University,
Seoul, Republic of Korea, in 1990, and his M.S. and Ph.D. degrees in electrical engineering
from the University of Arizona, Tucson, AZ, USA, in 1994 and 1997, respectively. From
1992 to 1997, he worked as a Research Associate at the SEMATECH Center. In 1997, he
joined LG Semiconductor (currently SK Hynix) as a Senior Researcher and later worked
at the LG Display Research Center from 1998 to 2003. He also served as an external
lecturer at Korea University in 2000 and as a Research Professor at Kyoto University,
Japan, from 2001 to 2002. In 2004, he joined the Department of Electronic and Electrical
Engineering, Dankook University, where he is currently a Professor. His research interests
include organic/inorganic hybrid semiconductor materials, high-efficiency photovoltaic
devices such as perovskite solar cells, and advanced sensors including photodetectors
and X-ray detectors.
Yong-Seo Koo received the B.S., M.S., and Ph.D. degrees from the Department of Electronic
Engineering from Sogang University, Seoul, Republic of Korea, in 1981, 1983, and 1992,
respectively. From 1983 to 1993, he had worked at Electronics Telecommunications Research
Institute as a senior researcher. In 2009, he joined the Department of Electronics
and Electrical Engineering, Dankook University as a Professor. His research interests
include electrostatic discharge (ESD) protection circuit design, silicon carbide (SiC)
power device, high-efficiency power management integrated circuits (PMICs).