I. INTRODUCTION

Gallium nitride (GaN) high electron mobility transistors (HEMTs) have been widely investigated for power electronics and RF applications due to their wide bandgap (3.4 eV), high electron mobility, and high breakdown voltage (BV) ^{[1- 8]}. Such material properties allow GaN HEMTs to achieve higher power density, faster switching, and greater efficiency than conventional silicon-based devices ^{[9- 13]}. These advantages make Metal-Insulator-Semiconductor (MIS) GaN HEMTs attractive for high-voltage and high-efficiency power applications. However, MIS-GaN HEMTs still suffer from strong electric field (e-field) crowding at the gate-to-drain edge under high drain bias conditions as shown in Fig. 1(a) ^{[14- 18]}. This phenomenon is caused by the sharp curvature at the gate edge, which induces a non-uniform potential distribution and leads to e-field crowding in the gate-to-drain region ^[19]. This highly localized e-field results in excessive gate leakage current and restricts the use of GaN HEMTs in high voltage applications. To mitigate this problem, field-plate (FP) structures shown in Fig. 1(b) have been widely adopted to distribute the e-field and suppress gate leakage ^{[20- 24]}. However, FP integration inevitably increases parasitic capacitance due to the extended gate-to-drain overlap ^{[25- 29]}. This parasitic capacitance leads to increased switching losses and complicates device optimization for power applications ^{[30- 34]}. In contrast, sidewall spacers formed at the gate edge provide an effective means to reshape the gate profile and mitigate e-field crowding near the gate-to-drain edge, without the need for additional FP. In this work, we propose and investigate a silicon nitride (Si₃N₄) sidewall structure integrated at the gate edge of MIS-GaN HEMTs. The effectiveness of the proposed structure is evaluated through TCAD simulation using parameters extracted from capacitance-voltage (C-V) and transmission line method (TLM) measurements of fabricated MIS-GaN HEMTs, and the transfer and output characteristics were calibrated to the measured devices, as shown in Fig. 2. The proposed structure is to employ a sidewall spacer that reshapes the gate edge profile and alleviates the sharp curvature. By modifying the gate geometry, the sidewall distributes the e-field in the gate-to-drain region and thereby reduces e-field crowding. This approach is intended to achieve these benefits without compromising the intrinsic device characteristics. These findings confirm that gate edge sidewall engineering can effectively suppress e-field crowding and leakage current, thereby offering a promising design strategy for achieving high breakdown capability and improved reliability in GaN HEMTs.

Fig. 1. Cross-sectional views of GaN HEMT structures. (a) Conventional MIS-GaN HEMT with electric field concentration near the gate edge. (b) Field plate (FP)-integrated structure for electric field distribution improvement.

Fig. 2. (a) Structural dimensions of the fabricated reference MIS-GaN HEMT without sidewall spacer. (b) Measurement-based parameter extraction from CV and TLM (c) Calibration results of transfer and output curves comparing experiment and simulation.

II. SIMULATION SETUP

The TCAD simulations were calibrated to match the measured characteristics of the fabricated MIS-GaN HEMTs. Surface donor-like interface traps were extracted from AC C-V measurements using the frequency-dependent conductance method ^[35]. In this approach, the onset voltage of the second rising slope in the AC-CV curves was tracked as a function of measurement frequency, and the resulting frequency-dependent shift was analyzed to obtain the corresponding trap energy range and interface-trap density. Through this procedure, a donor-like trap density of $2.56 \times 10^{13}$ cm$^{-2}$ located at 0.39 eV below the conduction band edge was determined. The source/drain contact resistance was obtained from TLM structures as 121.1 m$\Omega$·cm$^2$, and these experimentally extracted values were used to fine-tune the TCAD parameters so that the simulated current characteristics match the measurements. The calibrated parameters and physical models are summarized in Tables 1 and 2.

III. DEVICE STRUCTURE & PROCESS FLOW

Fig. 3(a) illustrates a cross-sectional schematic of the conventional MIS-GaN HEMT, showing the fabricated device with a GaN/AlGaN channel grown on a silicon substrate. The device is designed with a gate length ($L_g$) of 10 $\mu$m a source-gate spacing ($L_{gs}$) of 5 $\mu$m, a gate-drain spacing ($L_{gd}$) of 15 $\mu$m, and a gate width ($W_g$) of 200 $\mu$m.

The epitaxial stack consisted of a 2 $\mu$m GaN buffer, a 175 nm GaN channel, and a 15.5 nm AlGaN barrier layer, a 2 nm undoped GaN cap layer. After RCA cleaning, the active area was patterned and etched by inductively coupled plasma - reactive ion etching (ICP-RIE) using a Cl₂/BCl₃ gas mixture for 40 seconds to form device isolation. The source/drain contacts were formed with Ti/Al/Ni/Au (20/120/55/45 nm) deposited by electron beam (e-beam) evaporation, followed by annealing at 860$^\circ$C for 90 seconds. A 26-nm thick HfO₂ gate dielectric was deposited on the device by atomic layer deposition (ALD), and the HfO₂ above the source and drain region was then selectively removed by ICP-RIE. Gate and pad electrodes were formed by depositing Ni/Au (320 nm). A Si₃N₄ passivation layer thickness of 350 nm was then deposited by plasma-enhanced chemical vapor deposition (PECVD) and etched by coupled reactive ion etching (CCP-RIE) with CF₄/O₂ gas mixture 90 seconds. Finally, Al/Au (370 nm) was deposited by e-beam evaporation to complete the device fabrication. As shown in Fig. 3(b), the sidewall HEMT follows the same process flow as the MIS-HEMT, with the sidewall formation step additionally included. The sidewall spacer formation process is illustrated in Fig. 3(c). A Si₃N₄ layer was deposited and patterned to define the gate, followed by an additional Si₃N₄ deposition and etching to form the sidewall. The gate metal was deposited, and the structure was completed by lift-off process.

Fig. 3. (a) Cross-sectional schematic view of conventional MIS GaN HEMT, (b) and Side-Wall HEMT. (c) Process flow illustrating the formation of sidewall spacers.

IV. RESULTS AND DISCUSSION

In conventional MIS-GaN HEMTs, the gate-to-drain edge is known to be the most critical region for e-field crowding. At this region, the high curvature of the gate corner leads to a strong localization of the e-field under high drain bias. The proposed sidewall HEMT structure modifies the gate-edge e-field distribution, thereby suppressing crowding at the gate-to-drain region. In this structure, the Si₃N₄ sidewall spacer has a lateral extension and vertical height of 0.1 $\mu$m each, and its outer corner is rounded with a radius of 0.3 $\mu$m. Fig. 4(a) shows the lateral e-field profile gate-to-drain edge at gate voltage ($V_{gs}$) = $-2$ V and drain voltage ($V_{ds}$) = 355 V. The conventional device exhibits a sharp peak of 20.13 MV/cm due to e-field crowding, whereas the sidewall-integrated device reduces the peak to 13.13 MV/cm, corresponding to a 34.8% reduction in e-field intensity. This result confirms that the proposed sidewall structure effectively relaxes the gate-to-drain edge e-field enhancement under BV conditions. Fig. 4(b) shows the impact-ionization rate along the 2DEG channel. In the sidewall device, the impact-ionization rate at the gate-to-drain edge is reduced compared with the conventional structure, consistent with the e-field mitigation in Fig. 4(a). The mitigation of the gate-to-drain edge field crowding makes the lateral electric field in the drift region slightly more uniform, which causes the channel region around $x = 20-30$ $\mu$m to exhibit a slightly higher impact-ionization rate than in the conventional device. However, this value remains much lower than the peak at the gate-to-drain edge and does not change the breakdown location or the breakdown voltage. These trends are further illustrated in the two-dimensional electric-field distributions shown in Fig. 5. In the conventional device, the peak e-field is highly concentrated at the gate corner, which critically affects the breakdown characteristics. In contrast the sidewall-integrated structure distributes the e-field toward the spacer region, resulting in a more uniform profile near the gate-to-drain edge. The output and transfer characteristics are investigated to confirm the intrinsic device behavior. Figs. 6(a) and 6(c) present output characteristics with $V_{ds}$ swept up to 10 V and $V_{gs}$ varied from $-2$ V to 2 V in 1 V steps for the conventional and sidewall devices, respectively. Both devices exhibit comparable output characteristics, with extracted $R_{on}$ (on-resistance) of 23.24 $\Omega$·mm and 23.26 $\Omega$·mm. Figs. 6(b) and 6(d) show the transfer characteristics of the conventional and sidewall structures at $V_{ds} = 1$ V. The conventional structure exhibits a maximum transconductance ($G_{m,max}$) of 27.55 mS/mm, while the sidewall-integrated structure demonstrates a comparable value of 27.09 mS/mm. These similar intrinsic electrical characteristics are consistent with the fact that the sidewall extends by about 0.1 $\mu$m on each side of the 10-$\mu$m gate, corresponding to about a 2% change in gate length. As a result, the 2DEG sheet density and mobility under the gate remain very similar in the two devices, and the sidewall mainly distributes the off-state electric field at the gate-to-drain edge region. Consequently, the proposed sidewall structure improves the breakdown voltage while maintaining nearly identical intrinsic electrical characteristics, with only a slight reduction compared to the conventional device. The BV characteristics of conventional and sidewall-integrated devices are compared in Fig. 7. The conventional MIS-GaN HEMT exhibits a BV of 373 V, while the sidewall device achieves 406 V, corresponding to an 8.8% improvement. This enhancement is attributed to the distribution of the e-field away from the gate corner, as demonstrated in Figs. 4 and 5, which reduces the peak e-field intensity at the gate-to-drain edge. As a result, the impact ionization is delayed, and the device sustains a higher drain bias before reaching breakdown. In addition to the improvement in BV, the gate leakage behavior near BV also shows a distinction between the two structures. As shown in the inset of Fig. 7, the conventional device exhibits a steep rise in gate leakage current as the BV point is approached, which is consistent with the strong e-field crowding at the gate-to-drain edge. In contrast, the sidewall-integrated structure significantly suppresses this leakage increase, indicating that the distributed e-field not only enhances the breakdown strength but also improves gate reliability under high voltage conditions. Table 3 summarizes the dependence of the breakdown and intrinsic electrical characteristics on the sidewall dimensions. When the lateral extension and height of the sidewall are increased from 0.1 $\mu$m to 0.3 $\mu$m, the BV remains at 406 V, while $R_{on}$ changes only slightly from 23.26 $\Omega$·mm to 23.21 $\Omega$·mm and $G_{m,max}$ from 27.09 mS/mm to 27.24 mS/mm, with $V_{th}$ fixed at $-1.42$ V. These results indicate that 0.1 $\mu$m sidewall is already sufficient to modulate the e-field at the gate-to-drain edge. Increase the sidewall thickness to induce no further change in the e-field peak at the gate-to-drain edge, and the channel potential profile does not change. These results demonstrate that the proposed sidewall approach provides an effective means of improving device reliability, while causing only a slight degradation in the intrinsic electrical characteristics.

Fig. 4. (a) Lateral electric field along the gate-drain edge at $V_{gs} = -2$ V and $V_{ds} = 355$ V, showing 34.76% peak electric field reduction from 20.13 to 13.13 MV/cm. (b) Impact ionization profiles for conventional and sidewall structures under same bias.

Fig. 5. Electric field distribution near the gate-drain edge for (a) the conventional structure and (b) the sidewall structure.

Fig. 6. Conventional structure (a) output curve and (b) transfer curve. Sidewall structure (c) output curve and (d) transfer curve.

Fig. 7. BV characteristics with 8.8% improvement by sidewall. Inset: Gate leakage rise near BV in conventional structure.

V. CONCLUSIONS

In this work, a sidewall structure was proposed and investigated to suppress e-field crowding in MIS-GaN HEMTs. The sidewall integration effectively reduced the peak e-field at the gate-drain edge by 34.8%, thereby alleviating impact ionization and mitigating gate leakage near breakdown. As a result, the BV was improved from 373 V to 406 V, corresponding to an 8.8% enhancement, while the output and transfer characteristics remained nearly identical to those of the conventional device. These findings confirm that sidewall engineering provides a practical design strategy to enhance breakdown performance and device reliability, with only a slight degradation in the intrinsic electrical characteristics.