Process Parameter Effects on the Electrical Characteristics of Bottom-gated IGZO TFT
Integrated Monolithically on CMOS Circuit
Seo Yong Chi1,2
Jong Wan Park1
Hi-Deok Lee2
Wan-Gyu Lee1
-
(National Nano Fab Center, Daejeon, Korea E-mail: sychi@nnfc.re.kr)
-
(Chungnam National University, Daejeon, Korea E-mail: sychi@o.cnu.ac.kr)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
TFT, IGZO, electrical characteristics, process parameters, N2 anneal, SIMS, X-ray photoelectron spectroscopy (XPS), transmission electron microscope (TEM)
I. INTRODUCTION
Since CdS TFT was developed in 1962, a lot of materials were suggested and tested
[1]. At display industries, conventional a-Si:H TFT was already commercialized. For the
next, amorphous metal oxide semiconductors (a-MOS) TFT were introduced and developed
widely due to their special characteristics like transparency, flexibility and low
temperature process. The applications of a-MOS TFT are not only display industries
but also sensors like as light, pressure, pH, gas and others. In addition, it can
be used for neuromorphic systems such as artificial synapse/neuron emulation.
Fig. 1 shows the IGZO-based TFT development timeline since 1930. Especially for the usages
of XR, AR and VR, the IGZO TFT array that drives each pixel is to be added to a CMOS
silicon back-end-of-line (BEOL) process as one of a-MOS TFTs. After finishing the
CMOS FEOL process, there is rooms for IGZO TFT to be located like as Fig. 2 [2].
To integrate IGZO TFT array monolithically on CMOS circuit, the NNFC 180 nm CMOS BEOL
process was used at this experiment to implement display backplanes that drive TFT
source current to the high-resolution OLED to set better brightness and hold the pixel
voltage for an entire frame with a lower leakage than the existing alternatives. The
pre-test was done to check any obstacles. The pre-test sequence was based on the CMOS
BEOL process and added to insert the IGZO TFT process steps such as TFT gate dielectric/IGZO
deposition, source/drain electrodes and top gate materials. The details were listed
at Table 1. From this pre-test, two findings were observed. One was the temperature of CMOS
ending the annealing process step as 400$^\circ$C, 30 minutes. The ambient is normally
N2 or H2 for curing dangling bond of silicon surface interface. The other was the slope of
intermediate metal interconnection, which is played as a bottom gate (BG) electrode.
At submicron technologies as a 180 nm or 130 nm node, the metals were used as a stack
of Ti/Al/Ti/TiN. However, due to the different etch rate of Al and Ti/TiN materials,
the Al metal layers were always shown as shapes to the Ti/TiN layers as shown in Fig. 3.
Fig. 1. A time axis diagram of the development of the IGZO-based TFT.
Fig. 2. A cross-sectional illustration of IGZO TFT based on a typical CMOS backplane.
Table 1. CMOS BEOL process with dual gate IGZO TFT .
Fig. 3. Metal Al profile of CMOS BEOL process to which IGZO TFT and the interconnection
metal configuration were added.
II. EXPERIMENT, RESULT AND ANALYSIS
1. Experimental items and Electrical results
The undercut profile of intermetal should be improved as tapered. To do this the stack
metal was changed and consisted of Ti/TiN only, removing Al.
Experimental conditions in this paper were described at Table 2. The first experiment item was the gate dielectric material. One was Al2O3 and the other was SiO2. The purpose of the gate dielectric material split was for dual gate TFT usage, that
was, bottom and top gate electrode at CMOS BEOL process integration. Al2O3 was for BG and SiO2 for top gate. Inter metal dielectric (IMD) at CMOS BEOL process was used at PE-Oxide
based SiO2 by chemical mechanical polishing (CMP).
The second experimental item was N2 anneal which was already described at the introduction in this paper.
The electrical results, Vg-Id curves after the experiments is shown in Fig. 4. There was a remarkable leakage current difference at the gate off state, Ioff, between
the N2_anneal and the No_N2_anneal at the Al2O3 dielectric condition. Ioff at the N2_anneal was lower than 1 nA and the one of the No_N2_anneal was 100 nA, this was 100 times higher than that.
The other finding is the steep and slow subthreshold slope which is related with the
subthreshold swing (SS) at the Al2O3 condition. The N2_anneal was steep and the No_N2_anneal was slow.
Regarding the PE-Oxide condition, the differences like as Ioff and SS are not shown
as remarkably as the Al2O3 case. However, the threshold voltage difference of N2_anneal (9.0V) and No_N2_anneal (23.0V) are shown severely. It might be caused of another reason.
Table 2. Experimental split table.
|
Experiment
|
01
|
02
|
03
|
04
|
|
Bottom Gate Material
|
Ti/TiN
|
|
Bottom Gate Dielectric
|
Al2O3 (200 Å, ALD)
|
SiO2 (1000 Å, PE-Oxide)
|
|
IGZO
|
1000 Å
|
|
IGZO Anneal (N2, 400$^\circ$C, 30 min)
|
O
|
skip
|
skip
|
O
|
|
Source/Drain material
|
Molybdenum
|
Fig. 4. The electrical results of this experiment (a) Al2O3 and (b) PE-Oxide.
2. Analysis
2.1 Structural analysis by TEM
To figure out the possible causes, the first attempt was to check whether there were
any abnormal things at the TFT structures or not. It was formed well of each part
as BG electrode (Ti/TiN), Gate dielectric material (Al2O3 or SiO2), IGZO and Source/drain electrode (Mo). In Fig. 5, TEM cross section of each experimental condition is shown. There was no irregular
shape except for a dioxide crack at the sample (d), which could bring a direct electric
short between BG and source node of TFT. However, the Vg-Id curve of the sample (d)
did not show any direct shorts at each electric node.
Fig. 5. TEM cross section of each split sample (a) N2_anneal at Al2O3, (b) No_N2_anneal
at Al2O3, (c) No_ N2_anneal at PE-Oxide, (d) N2_anneal at PE-Oxide.
2.2 Oxygen binding energy by XPS
To analyze oxygen vacancy change depending on N2 anneal process, XPS measurement was fulfilled at the Al2O3 samples as shown in Fig. 6 and Table 2. The O1s peaks are classified as the low binding energy (LP), middle binding energy
(MP), and high binding energy (HP) according to references [3-
11]. The LP is interpreted as an indicator of oxygen atom amounts, O2- surrounded by In/Ga/Zn atoms [4-
6]. The MP is related with oxygen vacancies, O2- in oxygen deficient [7,
8]. The HP is belonged to chemisorbed, dissociated oxygen or OH- groups like as -CO3, adsorbed H2O or adsorbed O2
[9-
11].
At IGZO internal free electron generation mechanism, the metal cation (M) and the
ionized oxygen vacancy (V''o) behaves the following expression:
A finding is MP area decreasing from 8.3% to 5.9% by N2_anneal process, which meant to the reducing of the amount of V''o according to the expression (1). This is the reason why Ioff (< 1 nA) of N2_anneal condition at Id-Vg curve was 100 times lower than that (< 100 nA) of No_N2_anneal. Those vacancies normally act as shallow donor, supplying free electrons that
make the channel easier to turn on. With fewer donors, we need a large positive bias
(+0.4 V) to induce the same electron density in the channel, as can be seen in Fig. 4(a). Free carrier concentration changes the flat band and threshold voltage (Vth). If
Vth follows a logarithm of donor density, $\Delta$Vth can be expressed by the following
expression as a first approximate estimate:
It is well matched with the experimentally measured value. For many MOS-like models,
a change in doping that changes channel charge produces a logarithmic shift in Vth,
which is connected to off current that is dominated by subthreshold conduction or
exponential dependence on gate-voltage relative to Vth. Therefore, Ioff can be represented
by the following expression:
Finally combining (3) and (2) gives the following:
where SS is the subthreshold swing, Vo being the vacancy concentration.
In addition, from the fact of MP area reduction, we could interpret the IGZO layer
changed to more semiconductor like state from semi-metal state of No_N2_anneal condition.
Fig. 6. The normalized intensity vs. Oxygen binding energy by XPS, (a) No_N2_anneal,
and (b) N2_anneal of the Al2O3 samples.
Table 3. Peak position and relative area ratio of the LP, MP and HP peak at O1s scan
data of XPS measurement.
|
|
Peak position (eV) and area (%)
|
|
LP
|
MP
|
HP
|
|
No Anneal
|
530.38
|
531.79
|
532.56
|
|
70.0
|
8.3
|
21.7
|
|
N2 Anneal
|
530.74
|
531.99
|
532.67
|
|
67.7
|
5.9
|
26.4
|
1. LP: an indicator of oxygen atom amounts, O2- surrounded by In/Ga/Zn atoms
2. MP: related with oxygen vacancies, O2- in oxygen deficient
3. HP: belonged to chemisorbed, dissociated oxygen or OH- groups like as -CO3, adsorbed H2O or adsorbed O2
2.3 OH change observation by m-SIMS
We measured two different areas of TFT as channel and source/drain metal region by
mass(m)-SIMS. No change found at channel region. However, at source/drain metal region,
it is observed that the OH is decreasing at the underneath of source/drain metal (Mo)
by N2 anneal condition as shown in Figs. 7 and 8.
At the interface between source/drain and metal (Mo) or on the surface of IGZO, OH
and electron generation mechanism is expressed:
Fig. 7. SIMS result at source/drain metal region.
Fig. 8. Enlargement of OH profile at source/drain metal (Mo).
Due to source/drain metal (Mo) thickness was 100nm, the OH amount and depth of SIMS
data are exactly matched like 475 c/s (102 nm) of the No_N2_anneal and 104 c/s (104 nm) of the N2_anneal at the underneath of Mo metal.
It could be interpreted as SS of TFT Id-Vg curve's improvement caused by this OH decreasing
of N2_anneal condition. As early described in this paper, the SS of the N2_anneal was much steeper than that of the No_N2_anneal. The SIMS profiles of OH- give density of interface trap charge (Nit, # of trap charges/cm2) with the help of standard sample by integrating the peak area, transforming the
areal density into the interface trap density (Dit, # of trap charges/cm2/eV), resulting in interface traps (Cit, equal to q x Dit, q being the charge quantity).
Electronically the reduction in Cit is directly correlated with the improvement in
SS with the following expression:
If we assume that uniform bulk is depletion-limited in the channel and the Debye approximation
is valid due to the fact that depletion width is smaller than film thickness (100
nm) of IGZO, then Cdep $\approx$ $\varepsilon_s/\lambda_D$, $\lambda_D = (\varepsilon_s\text{kT/q}^2\text{n})^{0.5}$
where Cdep is the capacitance of depleted channel, $\varepsilon_s$ is IGZO permittivity,
$\lambda_D$ is Debye length, n being the free carrier density or concentration. Finaly
SS can be expressed by the following again:
For the ultrathin IGZO TFTs where the entire film can fully deplete, the simple Debye
capacitance gives a correct dependence $\sqrt{\text{n}}$ and the main contribution
to SS comes from the Cit. The mechanism that connects OH- content to SS behavior is explained by 'subthreshold conduction' as elaborated in
the previous description of (2), (3), (4) for the correlation between the reduced MP and the improvement in the improvement
in Ioff.
2.4 IGZO composition ratio by TOF-SIMS
Compared to m-SIMS that could be measured only by the bulk samples, Time of flight
(TOF)-SIMS was useful for the real patterned TFT devices. Moreover, it was possible
to make 3D imaging of the TFT structure.
Related with IGZO composition ratio as In, Ga, and Zn elements, no difference is found
between each split condition by m-SIMS and TOF-SIMS.
Fig. 9. Top view by TOF-SIMS at (a) No_N2_anneal at Al2O3, (b) N2_anneal at Al2O3,
(c) estimated areas of each nodes.
Fig. 10. 3D imaging by TOF-SIMS at (a) XY view, and (b) each element such as Si, Ti,
Al, In, and Mo.
2.5 IGZO roughness by AFM
Finally, we checked the IGZO roughness by AFM (Atomic Force Microscopy). The measured
value is 0.468 nm (rms) at the N2_anneal process and 0.489 nm (rms) at the No_N2_anneal. According to these data, we concluded that the IGZO surface roughness was
not changed and no influence for the electrical results.
Fig. 11. AFM data at (a) No_N2_anneal, and (b) N2_anneal .
III. CONCLUSIONS
We studied the process parameter effects on the electrical characteristics of bottom
gated IGZO TFT integrated monolithically on CMOS circuit. Due to the limitation of
CMOS BEOL compatible process, the 400C, 30 minutes N2 anneal should be adapted. However, the anneal process brought the electrical influence
positively and analyzed why these improvements happened through the various tools
such as TEM, XPS, mass SIMS, TOF-SIMS and AFM. Especially for XPS analysis, it turned
out to be that the relative area ratio of MP at Oxygen played an important role of
Ioff characteristics of IGZO TFT. Also, the OH density of interface between the source/drain
metal and IGZO layer influenced SS slope of TFT. It meant that the process treatment
before the source/drain metal sputtering should be carefully managed.
IV. FUTURE WORKS
Our next step is the ambient experiment of the anneal process like N2, O, H2, Air and Vacuum as well as the anneal temperature. The composition ratio of IGZO
also will be experimented.
ACKNOWLEDGEMENTS
This work was supported by National Nano Fab Center in Korea.
REFERENCES
Zhu Y. , He Y. , Jiang S. , Zhu L. , Chen C. , Wan Q. , 2021, Indium–gallium–zinc–oxide
thin-film transistors: Materials, devices, and applications, Journal of Semiconductors,
Vol. 42, No. 3, pp. 031101

Kaçar R. , Serin R. B. , Uçar E. , Artuç M. , Ülkü A. , Kınacı B. , 2025, OLED-on-silicon
(OLEDoS) microdisplays: Technology challenges, design considerations, and adaptation
in eXtended Reality (XR) ecosystem, Next Nanotechnology, Vol. 7, pp. 100132

Park S. , Bang S. , Lee S. , Park J. , Ko Y. , Jeon H. , 2011, The effect of annealing
ambient on the characteristics of an indium–gallium–zinc oxide thin film transistor,
Journal of Nanoscience and Nanotechnology, Vol. 11, No. 7, pp. 6029-6033

Rao L. K. , Vinni V. , 1993, Novel mechanism for high speed growth of transparent
and conducting tin oxide thin films by spray pyrolysis, Applied Physics Letters, Vol.
63, No. 5, pp. 608-610

Cebulla R. , Werndt R. , Ellmer K. , 1998, Investigation of reactive magnetron sputtered
zinc oxide films, Journal of Applied Physics, Vol. 83, No. 2, pp. 1087-1095

Bang S. , Lee S. , Park J. , Park S. , Jeong W. , Jeon H. , 2009, Investigation of
the effects of interface carrier concentration on ZnO thin film transistors fabricated
by atomic layer deposition, Journal of Physics D: Applied Physics, Vol. 42, No. 23,
pp. 235102

Chen M. , Pei Z. L. , Sun C. , Wen L. S. , Wang X. , 2000, Surface characterization
of transparent conductive oxide Al-doped ZnO films, Journal of Crystal Growth, Vol.
220, pp. 254-262

Fan J. C. C. , Goodenough J. B. , 1977, X-ray photoemission spectroscopy studies of
Sn-doped In2O3 films, Journal of Applied Physics, Vol. 48, No. 8, pp. 3524-3531

Lee S. , Bang S. , Park J. , Park S. , Jeong W. , Jeon H. , 2010, The effect of oxygen
remote plasma treatment on ZnO TFTs fabricated by atomic layer deposition, Physica
Status Solidi (a): Applications and Materials Science, Vol. 207, No. 8, pp. 1845-1849

Islam M. N. , Ghosh T. B. , Chopra K. L. , Acharya H. N. , 1996, XPS and X-ray diffraction
studies of aluminum-doped zinc oxide transparent conducting films, Thin Solid Films,
Vol. 280, pp. 20-25

Nomura K. , Kamiya T. , Yanagi H. , Ikenaga E. , Yang K. , Kobayashi K. , Hirano M.
, Hosono H. , 2008, Subgap states in transparent amorphous oxide semiconductor, In–Ga–Zn–O,
observed by bulk sensitive X-ray photoelectron spectroscopy, Applied Physics Letters,
Vol. 92, No. 20, pp. 202117

Lee S. , Bang S. , Park J. , Park S. , Jeong W. , Jeon H. , 2010, The effect of oxygen
remote plasma treatment on ZnO TFTs fabricated by atomic layer deposition, Physica
Status Solidi (a): Applications and Materials Science, Vol. 207, No. 8, pp. 1845-1849

Seo Yong Chi received the B.S. degree in physics from Hanyang University in 1989.
He joined to develop DRAM cell design at Process Development department of R&D center,
Hyundai Electronics Ind. Co., Ltd, current SK Hynix in 1990. In Magnachip, current
SK Key Foundry, he experienced with high voltage devices from 12 V to 250 V, and automotive
technology imbedded NVM (Non-Volatile Memory) until 2016. He also worked at Silanna,
focusing on power products, its head quarter based on San Diego, C.A in US until 2023.
As a Research Fellow, he is supporting at National NanoFab Center (NNFC). His research
interests include the development of high voltage devices such as LDMOS, and VDMOS,
NVM, and wide band gap semiconductors like silicon carbide (SiC), gallium nitride
(GaN), and a-MOS including IGZO.
Jong Wan Park received the Ph.D. degree in physics from Chungbuk National University
in 2001. He joined the National Nano Fab Center (NNFC) in 2005. His research interests
include the development of convergence technologies such as nano-electronic devices,
nano-biosensors, nano-sensors, CMOS, and MEMS.
Hi-Deok Lee received the B.S., M.S., and Ph.D. degrees from the Korea Advanced Institute
of Science and Technology, Daejeon, South Korea, in 1990, 1992, and 1996, respectively,
all in electrical engineering. In 1993, he joined SK Hynix Semiconductor (formerly
LG Semicon), Cheongju, South Korea, where he was involved in the development of 0.35-,
0.25-, and 0.18 $\mu$m CMOS technologies, respectively. He was also responsible for
the development of 0.15- and 0.13 $\mu$m CMOS technologies. Since 2001, he has been
with Chungnam National University, Daejeon, and currently a Professor with the Department
of Electronics Engineering. From 2006-2008, he was with the University of Texas at
Austin and SEMATECH, Austin, as a Visiting Scholar. He also has been CTO of Korea
Sensor Lab Co., Ltd., since 2012. His research interests are nanoscale CMOS technology
and its reliability physics, silicide technology, and test element group design and
development of neuromorphic semiconductor devices. His research interests also include
the development of high performance sensors. He was a recipient of the Excellent Professor
Award from Chungnam National University in 2001, 2003, and 2014. He also received
a minister prize and presidential award in 2018 and 2019, respectively. He has been
a member of the Institute of Electronics and Information Engineer since 1988 and a
member of the IEEE since 1992.
Wan-Gyu Lee received the Ph.D. degree in Metallurgical engineering from Seoul National
University, Seoul, South Korea in 1997. He joined Hyundai Electronics Ind. Co., Ltd.
Korea (currently, SK Hynix Semiconductor Ltd.) His research interests include development
of convergence technology such as CMOS & Biology, CMOS & MEMS, CMOS & Sensors, and
Si photonics for next-generation platforms. He has been working at National NanoFab
Center (NNFC) since 2005.