A 1.12-ps Resolution Flash ADC-assisted Coarse-to-fine Time-to-digital Converter with
Adaptive Reference-voltage Calibration and Digital Linearity Correction
ShinSolmon1
SonHyunwoo1
KimYoungsik1
KimShinwoong1
-
(Department of Computer Science and Electrical Engineering, Handong Global University,
Pohang, Gyeongbuk 37554, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Time-to-digital converter (TDC), coarse-to-fine-conversion architecture, ADC-assisted TDC, reference-voltage calibration, digital linearity correction
I. INTRODUCTION
With continued scaling of semiconductor processes and the advancements in circuit
integration, digital-intensive circuits and systems, where various signal processing
and control operations are performed in the digital domain, have been actively developed.
Therefore, the importance of analog-to-digital conversion circuits has increased.
In particular, the time-to-digital converter (TDC), which converts an input time interval
into a digital output code, serves as a critical building block and is widely employed
in applications such as autonomous driving, optical communications, distance sensing,
image sensing, and RF frequency synthesis [1-4].
In RF frequency synthesizers for high-frequency carrier generation, the TDC converts
the time difference (phase error) between the reference clock and the feedback oscillator
signal into a digital code. The characteristics of this conversion directly affect
the phase noise and jitter performance of the synthesizer. Therefore, to achieve precise
time measurement, a high-resolution and high-linearity TDC is required.
Traditional delay-line-based TDCs offer a simple structure but are highly sensitive
to variations in temperature, supply voltage, and process (PVT). Although Vernier
delay lines can achieve higher resolution, they require an excessive number of delay
cells to support a wide input dynamic range [5]. To address these limitations, ring oscillator-based TDCs have been introduced. The
ring oscillator oscillates for the duration of the input time error, and a counter
accumulates the resulting edges, thereby providing a wide dynamic range. Furthermore,
by utilizing the multi-phase outputs of the ring oscillator, sub-counting resolution
can be achieved [6]. To achieve higher resolution, a fine-conversion method has been proposed, in which
an analog-to-digital converter (ADC) is employed as an assist circuit to convert the
time error down to the sub-phase level [7]. However, the fine conversion process based on a successive approximation register
(SAR) ADC, as adopted in previous works, suffers incurs long conversion latency, which
limits its applicability to frequency synthesizer systems operating with a high-speed
reference clock.
To overcome this limitation, this paper introduces a flash ADC in the fine conversion
stage to enhance the overall conversion speed. The ring oscillator operates during
the input time error interval and stops oscillating at the end of this interval. At
the stopping point, two adjacent phase signals are sampled and applied to the flash
ADC. These signals are digitized by the flash ADC in synchronization with the operating
clock, enabling fine conversion with sub-phase resolution. The proposed architecture
in this work is based on a ring oscillator and utilizes the analog voltages of each
oscillator phase for fine conversion. In such architectures, linearity becomes a critical
design consideration.
Skew among the oscillator phases can arise because of layout mismatches, device mismatches,
and variations in process, voltage, and temperature (PVT). This skew produces unequal
peak voltages among the phases used for fine conversion, causing variations in inter-phase
voltage ratios and, in turn, non-uniform TDC code spacing. As a result, the overall
linearity of the TDC is degraded. To address these issues, this work proposes a calibration
circuit that dynamically sets the reference voltage of the flash ADC based on the
averaged peak voltages across the oscillator phases, mitigating the effects of non-uniform
peak voltages. In addition, to compensate for residual nonlinearity within each phase
interval, this work divides each phase into four sub-phase regions and applies a digital
linearity correction accordingly.
The proposed TDC was implemented in a 28nm CMOS process, and its performance was verified
through post-layout simulations. The TDC achieves a precise time resolution of 1.12
ps, a wide dynamic range of 63 ns, and a conversion time of 5.6 ns, enabling high-speed
operation. In terms of linearity, the TDC achieves a differential non-linearity (DNL)
of ±1.5 LSB and an integral non-linearity (INL) of ±5 LSB. The TDC core occupies an
area of 0.6 mm2 and consumes 5.42 mW, indicating high integration density and power efficiency. This
paper is organized as follows. Section II provides an overview of the proposed TDC
architecture. Section III describes the calibration techniques for linearity enhancement.
Section IV presents the post-layout simulation results and Section V concludes this
work.
II. ARCHITECTURE
1. Overview of Architecture
Fig. 1 illustrates the overall block diagram of the proposed time-to-digital converter (TDC).
The core building blocks comprise a phase-frequency detector (PFD), ring oscillator,
counter, comparator, analog-to-digital converter (ADC), and calibration circuitry.
Employing a ring-oscillator-based architecture, the TDC achieves a wide input dynamic
range, while an ADC-assisted fine conversion stage enables high time resolution. In
this stage, a flash ADC is employed to shorten the conversion time, and reference
voltage calibration and a digital linearity correction circuit are incorporated to
enhance overall linearity.
Fig. 1. Block diagrams of the proposed flash ADC-assisted coarse-to-fine TDC.
The coarse conversion of the TDC is performed in the digital domain by a ring oscillator,
counter, and encoder. As shown in Fig. 2, the ring oscillator oscillates for the time interval between the START and STOP
signals while EN_RO is high. During this interval, the counter increments its value
on each rising edge of the ring-oscillator output, performing the first (coarse) conversion.
When EN_RO goes low, the ring oscillator stops oscillating, and the encoder reads
the 13-phase outputs, thereby completing a second conversion with sub-counter-level
precision. Finally, at the falling edge of EN_RO, two adjacent ring-oscillator phase
nodes are selected, and a flash ADC performs the fine conversion in the analog domain
with sub-phase resolution. All conversion stages are coordinated by control signals
generated by the timing controller, while the START and STOP signals serve as the
global reference for the entire time conversion.
Fig. 2. Timing diagram of the coarse conversion.
2. Coarse TDC
The coarse-conversion stage of the TDC digitizes the interval between the START and
STOP pulses through a sequence of operations. A phase-frequency detector (PFD) followed
by an XOR gate generates an enable pulse, EN_RO, whose width equals the START-to-STOP
delay. While EN_RO is high, a 13-phase ring oscillator (RO) oscillates, and the first
phase output, P[0], clocks an up counter, producing an initial coarse code with a
resolution of one RO period.
As shown in Fig. 3, when the STOP pulse arrives, EN_RO transitions to low, halting the 13-phase ring
oscillator and holding the instantaneous voltages of its phase nodes P[0]-P[12]. Each
phase node is first buffered by a source follower (SF), converted to differential
form by a resistive interpolator, and then quantized by a bank of 13 comparators,
producing a 13-bit thermometer code. By analyzing the 13-bit thermometer code, the
two adjacent phases—P[i] and P[i + 1]—that straddle the STOP instant are identified.
Consequently, the coarse-conversion resolution is limited to one-thirteenth of the
ring-oscillator period.
In this work, a 13-phase ring oscillator is employed; hence, one ring-oscillator period
is partitioned into 13 ZONEs. The counter output increases linearly during the EN_RO
pulse, whose width encodes the input time interval, whereas the ZONE index repeats
from 0 to 12 whenever the counter increments by one. To obtain the final coarse code,
the two quantities are combined:
However, when the counter value and the ZONE index are combined, a timing mismatch
can arise owing to the propagation-delay difference between the two signal paths.
As illustrated in Fig. 4, any misalignment between the counter-increment instant and the ZONE-index wrap-around
instant can introduce a time error of up to one ring-oscillator period in the final
coarse code. To compensate for the timing mismatch, the proposed TDC employs both
phase P[0]—used as the counter clock—and phase P[2].
Because the mismatch occurs exactly when the counter increments, we resolve it by
selecting the counter value sampled by a later RO phase (i.e., one or more phases
after the boundary). Although P[1] is sufficient, we choose P[2] (≈2/13 of one RO
period later) to increase the path delay margin and improve tolerance to PVT-induced
skew. As a result, the architecture retains the 13-ZONE time resolution—one-thirteenth
of a ring-oscillator period—while simultaneously covering the wide dynamic range provided
by the counter.
Fig. 4. TDC transfer curve (a) without counter-ZONE propagation-delay compensation
and (b) with compensation.
3. Fine TDC
After the coarse conversion, a fine-conversion stage is executed to achieve sub-phase
resolution. In this work, the fine conversion is carried out in the analog domain
using an on-chip ADC, and the architecture is optimized for high-speed reference-clock-driven
frequency synthesizers by minimizing conversion latency. A flash ADC is therefore
employed, enabling the sub-phase interval to be digitized in a single conversion cycle
and providing the required fine resolution. As illustrated in Fig. 5, when the STOP signal arrives, the ring oscillator is halted and the voltages of
the two adjacent phases at that instant, P[i] and P[i + 1], are simultaneously applied
to two 6-bit flash ADCs. The resulting digital outputs, ADC_OUT1 and ADC_OUT2, vary
linearly with the input time error. Exploiting this linearity, a ratio-based fine-conversion
algorithm is employed to estimate the precise sub-phase position within each ZONE.
The proportional equation determines the relative position of ADC_OUT2 by taking the
difference between the two flash-ADC codes. Because the resulting fine ratio increases
linearly with the input time error, the timing position can be further refined within
the ZONE determined by the coarse conversion, thereby achieving sub-phase resolution.
The theoretical time resolution attainable in the fine-conversion stage is defined
as follows:
Because a 6-bit flash ADC is employed, the fine stage can theoretically provide an
additional time resolution equal to 1/32 of the coarse step. Realizing this limit
requires the ring-oscillator output to approximate a sinusoidal waveform. For this
purpose, a skewed-inverter ring oscillator is adopted. This topology increases the
oscillation frequency with a limited number of stages and, consequently, delivers
quasi-sinusoidal phase signals [8]. To provide a stable drive for the differential comparators and to enhance output
linearity, a resistive interpolator is additionally incorporated. This scheme improves
the input-output linearity of the fine-conversion stage.
Fig. 6 presents the timing diagram of the control signals that govern the overall TDC operation.
The time interval between the rising edges of the START and STOP pulses is translated
into the enable signal EN_RO. At the falling edge of EN_RO, a sequence of enable pulses
is issued to the coarse- and fine-conversion blocks. All control lines are precisely
generated and aligned by the timing controller, ensuring that each stage operates
at the correct instant. The entire conversion sequence is completed within approximately
5.6 ns after the STOP edge.
Fig. 6. Timing diagram of the proposed TDC.
III. LINEARITY IMPROVEMENT TECHNIQUES
1. Adaptive Reference-voltage Calibration
The high-performance operation of the proposed TDC relies on accurately exploiting
the multi-phase outputs of the ring oscillator in both the digital and analog domains.
Achieving this goal requires tight phase alignment and a linear output waveform across
the oscillator phases. In practice, however, phase skew is inevitably introduced by
process, voltage, and temperature (PVT) variations and by load mismatches caused by
interconnect parasites during chip implementation and layout. This phase skew is one
of the main sources of non-linearity in the TDC conversion process. Fig. 7 illustrates the presence of skew among the ring-oscillator phases. In the coarse-conversion
stage, timing skew makes the ZONE widths non-uniform, while in the fine stage it causes
the voltage range applied to the ADC to differ from one ZONE to another. These effects
degrade both the accuracy and the linearity of the overall conversion.
Fig. 7. Peak voltage variation at the ADC input caused by ring oscillator phase skew.
Fig. 8 illustrates how ZONE-width non-uniformity, induced by phase mismatch in the ring
oscillator, distorts the fine-conversion result. With the ADC reference voltage set
for the ideal ZONE width, Figs. 8(a) and 8(b) show, respectively, the cases in which the actual input voltage range is excessive
or insufficient. In Fig. 8(a), the width of a particular ZONE is larger than ideal; the resulting voltage range
delivered to the ADC exceeds the reference-voltage window, driving the ADC output
code into saturation. By contrast, Fig. 8(b) depicts a ZONE that is narrower than ideal, so the input voltage does not reach the
upper reference level, producing a sharp code discontinuity and a highly nonlinear
response at the ZONE boundary.
Fig. 8. TDC transfer curve with reference voltage for the ideal ZONE width (a) ZONE
wider than ideal and (b) ZONE narrower than ideal.
To address the non-linearity introduced by phase skew among the ring-oscillator phases
in the fine-conversion stage, this paper proposes an adaptive reference-voltage calibration
technique. During a pre-operation calibration phase, the procedure measures the peak
voltage delivered to the ADC in each ZONE, averages these peaks, and sets the resulting
value as the reference voltage. In this way, the ADC reference-voltage window is adaptively
aligned to the ZONE-dependent input range, mitigating the skew-induced error.
Fig. 9 shows the proposed calibration loop, which consists of a peak detector, a comparator,
a delta-sigma modulator (DSM), and a 1-bit digital-to-analog converter (DAC). The
peak detector first captures the maximum of the ADC input voltage in each ZONE and
feeds this value to the comparator, where it is compared with the present reference
voltage. The comparator output is processed by DSM and the 1-bit DAC, which gradually
drives the reference voltage toward the average of the measured peaks.
Fig. 9. Proposed adaptive reference-voltage calibration circuit.
Because the loop operates in feedback, the reference voltage is adjusted dynamically
with the applied time error and therefore adapts to the actual voltage distribution
of each ZONE. This adaptation improves the output linearity of the flash ADC and,
in turn, enhances the resolution of the fine-conversion stage. Moreover, the proposed
circuit supports not only foreground calibration but also background calibration while
the TDC is running, allowing real-time compensation for PVT variations.
2. Digital Linearity Correction
The adaptive reference-voltage calibration described earlier mitigates comparator
saturation and improves overall linearity by setting the reference level to the average
peak voltage measured in each ZONE. Because the same reference is applied to all ZONEs,
however, it cannot fully remove the residual non-linearity that arises from the unequal
time spacing of the ZONEs themselves. For example, even after calibration, certain
ZONEs can still drive the ADC into saturation or exhibit a nonlinear response, thereby
distorting the fine-conversion result and degrading the accuracy of the TDC output
code.
To precisely compensate for the residual nonlinearity, we adopt a digital linearity-correction
scheme that exploits the flash-ADC digital output, as shown in Fig. 10, and we form sub-ZONEs according to the encoding concept in Fig. 11. The 13 ring-oscillator ZONEs are each subdivided into four sub-ZONEs, yielding 52
sub-ZONEs in total. In a foreground calibration step, the input time error is swept
in one-resolution increments (1 LSB), and the resulting TDC codes are analyzed on
a per-sub-ZONE basis to determine a signed code offset that minimizes local nonlinearity.
The offsets are stored in a lookup table (LUT). During normal operation, the flash-ADC
code identifies the active sub-ZONE, and the corresponding LUT offset is algebraically
added to or subtracted from the raw TDC output code, thereby correcting the sub-ZONE
dependent error and improving the overall conversion accuracy.
Fig. 10. Digital linearity correction circuit.
Fig. 11. Sub-ZONE encoding.
Furthermore, although the calibration described in this work is performed in an open-loop
TDC environment and thus constitutes foreground calibration, the same approach can
be extended to background calibration when the TDC is embedded in a PLL (closed-loop)
system. In that case, the TDC output in closed loop can be used to estimate and update
the per-sub-ZONE offsets in real time, enabling continuous correction without interrupting
normal operation and allowing online tracking and compensation of PVT-induced nonlinearity.
IV. SIMULATION RESULTS
The proposed flash-ADC-assisted coarse-to-fine TDC was designed in a 28 nm CMOS process;
the complete layout is shown in Fig. 12. The circuit dissipates 5.42 mW during operation and occupies an effective core area
of approximately 0.645 mm2. Figs. 13-15 present post-layout simulation results that verify the linearity-improvement techniques.
Differential non-linearity (DNL), integral non-linearity (INL), and the TDC output-code
response were evaluated under three calibration conditions to quantify the performance
gains achieved by each correction stage.
Fig. 12. Layout view of TDC implemented using 28-nm CMOS process.
In this work, one least significant bit (LSB) corresponds to the fine-conversion step
of one ADC code, yielding an effective resolution of 1.12 ps. Fig. 13 plots the simulated differential non-linearity (DNL) and integral non-linearity (INL)
when the flash-ADC reference voltage is fixed to the ring-oscillator supply, RO_VDD.
With the reference held constant, DNL and INL enlarge to ±12 LSB, exposing the severe
non-linearity produced by unequal ZONE spacing. Repetitive DNL spikes and a saw-tooth
INL drift at every ZONE boundary highlight the need for calibration.
Fig. 13. Simulated DNL and INL without calibration.
The benefit of the proposed adaptive reference-voltage calibration is demonstrated
in Fig. 14. After calibration, DNL and INL improve to ±3.8 LSB and ±8.9 LSB, respectively, indicating
that dynamically aligning the reference voltage to the ZONE-dependent input range
suppresses ADC saturation and code discontinuities.
Fig. 14. Simulated DNL and INL with adaptive reference voltage calibration.
To cancel the remaining error, a sub-zone digital linearity-correction is subsequently
applied. As shown in Fig. 15, DNL and INL are further reduced to ±1.5 LSB and ±5.0 LSB. The two-step approach—reference
voltage calibration followed by digital post-processing—therefore yields a substantial
improvement in the overall linearity of the TDC.
Fig. 15. Simulated DNL and INL with adaptive reference voltage calibration and digital
linearity correction.
The effectiveness of the proposed calibration chain is also evident in the TDC transfer
characteristics. Fig. 16 plots the TDC output code versus input time error for the three calibration stages.
In Fig. 16(a), without any calibration, the output code changes discontinuously at each ZONE boundary,
producing a pronounced stair-step non-linearity. After the adaptive reference-voltage
calibration (Fig. 16(b)), the response becomes smoother, with a more uniform overall slope and substantially
reduced discontinuities at the ZONE edges. When both the reference-voltage calibration
and the digital linearity correction are enabled (Fig. 16(c)), the TDC output increases almost linearly with a nearly constant slope over the
entire input-error range, approaching the ideal transfer characteristic.
Fig. 16. Simulated TDC transfer curve (a) without calibration, (b) with adaptive reference-voltage
calibration and (c) with adaptive reference-voltage calibration and digital linearity
correction.
In the simulation, the time interval between the START and STOP pulses was swept with
fine steps to generate the input time error, and the corresponding TDC output codes
were recorded to evaluate overall linearity and resolution. The proposed TDC achieves
an effective time resolution of 1.12 ps, a conversion time of 5.6 ns, and an input
dynamic range of 63 ns. These results demonstrate that architecture provides performance
suitable for high-speed frequency synthesizers and other systems that require precise
time measurement.
The performance of the proposed ADC-assisted TDC is summarized in Table 1 along with previously reported high-resolution TDCs. Compared with earlier works,
the design provides fine time resolution, faster conversion time, a wide conversion
range, and improved linearity through the proposed calibration technique, demonstrating
strong potential for integration into fractional-N PLLs, LiDAR time-of-flight sensors,
and other precision-timing applications.
Table 1. Performance summary and comparison.
|
|
This work
|
JSSC’12 [9] |
JSSC’13 [10] |
JSSC’14 [11] |
JSTS’15 [12] |
|
Resolution (ps)
|
1.12
|
1.25
|
1.76
|
1.12
|
0.15
|
|
Conversion rate (MHz)
|
178.57
|
100
|
300
|
250
|
-
|
|
Conversion range (ns)
|
63
|
1.25
|
1.8
|
0.58
|
0.64
|
|
DNL(LSB)
|
1.5
|
0.7
|
0.6
|
0.6
|
1.9
|
|
INL(LSB)
|
-3~+5
|
-3~+1
|
1.9
|
1.7
|
3.5
|
|
Power (mW)
|
5.42
|
4.3
|
-
|
15.4
|
4.32
|
|
Area (mm2)
|
0.645
|
0.07
|
-
|
0.14
|
0.5
|
|
Technology (nm)
|
28
|
130
|
130
|
65
|
180
|
V. CONCLUSIONS
This paper presents a ring-oscillator-based, flash-ADC-assisted coarse-to-fine time-to-digital
converter (TDC). By combining ZONE-encoded coarse conversion with a flash-ADC fine
stage, the architecture simultaneously achieves high resolution, a wide conversion
range, and short conversion latency. To counteract the ZONE-spacing non-uniformity
and fine-stage non-linearity caused by phase skew in the ring oscillator, an adaptive
reference-voltage calibration loop dynamically adjusts the flash ADC reference voltage.
In addition, each ZONE is subdivided into four sub-ZONEs, and a lookup-table-based
digital linearity-correction scheme removes the residual sub-ZONE non-linearity. The
TDC was implemented in a 28 nm CMOS process. Post-layout simulations confirm an effective
time resolution of 1.12 ps, a conversion time of 5.6 ns, and a conversion range of
63 ns, together with linearity of ±1.5 LSB (DNL) and ±5.0 LSB (INL). These results
demonstrate that the proposed structure is a suitable architecture for next-generation
data-conversion systems that require both high speed and sub-picosecond timing precision.
ACKNOWLEDGMENTS
This work was supported by the BK-21 FOUR program through the National Research Foundation
of Korea (NRF) under the Ministry of Education. The EDA tool was supported by the
IC Design Education Center (IDEC), Korea. This research was supported by No. 202400570001
(project number) of Handong Global University Research Grants.
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Solmon Shin received his B.S. degree in computer science and electrical engineering
from Handong Global University, Pohang, South Korea, in 2024, where he is currently
pursuing an M.S. degree. His research interests include time-to-digital converters,
analog/digital integrated circuits, phase-locked loops.
Hyunwoo Son received his B.S. and Ph.D. degrees in electrical engineering from Pohang
University of Science and Technology (POSTECH), Pohang, South Korea, in 2012 and 2019,
respectively. From 2019 to 2020, he was with the Institute of Microelectronics, Agency
for Science, Technology, and Research (A*STAR), Singapore, where he was involved in
the design of biomedical integrated circuits. In 2020, he joined Gyeongsang National
University, Jinju, South Korea, where he is currently an Associate Professor. His
research interests include sensor interface circuits, biomedical circuits, energy-efficient
hardware for neural networks, and energy management systems for hybrid power sources.
Youngsik Kim received his B.S., M.S., and Ph.D. degrees in electronic and electrical
engineering from the Pohang University of Science and Technology, Pohang, South Korea
in 1993, 1995, and 1999, respectively. Since then, he has been a professor in the
School of Computer Science and Electrical Engineering at Handong Global University.
His research focuses on the ultra-low power transceiver circuits, with additional
interests in the circuit design neural networks.
Shinwoong Kim received his B.S. and M.S. degrees in electrical engineering and information
and communication engineering from Handong Global University, Pohang, South Korea,
in 2009 and 2011, respectively, and a Ph.D. degree in electronic and electrical engineering
from the Pohang University of Science and Technology, Pohang, South Korea, in 2016.
From 2016 to 2022, he was a Senior Engineer at Samsung Electronics, Hwasung, South
Korea, where he involved in the design of Local Oscillator (LO) domain including all-digital
phase-locked loop for RF communication systems. In 2022, he joined Handong Global
University, Pohang, South Korea, where he is currently an Assistant Professor. His
current research interests include analog/digital frequency synthesizer and low-power
clock generation.