1. Operation of Vernier TDC

TDCs convert the time difference between two signals into corresponding digital codes. Conventional single-delay-line TDCs are limited by gate delay and cannot achieve fine resolution below that threshold. Vernier TDCs address this limitation by using two delay chains with delays τ₁ and τ₂ (τ₁ > τ₂), as illustrated in Fig. 1.

Given an initial time difference T between the start and stop signals, each delay stage reduces this difference by ΔT = τ₁ − τ₂. When the start signal leads the stop signal, the sampling registers produce high outputs. Conversely, if the stop signal leads, the time difference becomes negative, and the outputs transition to low. This operation enables Vernier TDCs to achieve a resolution of ΔT and generate digital thermometer codes corresponding to the original time difference T.

Fig. 1. Operation of conventional Vernier-based TDC.

2. Specification of the Proposed TDC for NAND Flash

The proposed TDC is designed for integration into the NAND Flash duty-cycle corrector (DCC) and meets the timing requirements of NAND Flash interfaces ^[1]. In these interfaces, signal quality is defined by tDIVW1 (DQ Rx Mask Timing Window at Vcent_DQ), which is specified as 0.48 UI. This accounts for approximately 4% duty cycle distortion from external sources, along with additional degradation from internal signal paths. To ensure proper operation, the DCC must compensate for up to 5% distortion, and the TDC must digitize the corresponding timing differences.

To support backward compatibility with legacy NAND Flash standards, the TDC must operate over data rates from 800 Mbps to 3.6 Gbps. This corresponds to a required time range of at least 125 ps at 800 Mbps and 28 ps at 3.6 Gbps. The TDC’s conversion range must cover this variation to ensure correction across supported speeds. In addition, the time resolution per bit of the TDC directly determines the DCC’s correction capability. To support 1% duty-cycle correction resolution, equivalent to 5.6 ps at 3.6 Gbps, the TDC is designed with a resolution below 5.6 ps.

The TDC operates at a sampling frequency of 100 MS/s to minimize DCC training time and enable fast initialization in high-speed NAND Flash systems, even though the NAND specification does not explicitly define a training time for DCC operation.

3. Proposed Two-Step TDC Architecture

Traditional Vernier TDCs require long delay chains to achieve the specified time range, creating design constraints in memory applications with strict area limitations. To address this, we propose a two-step TDC comprising two sequential delay loops, the Coarse Loop and the Fine Loop, as shown in Fig. 2(a). The circuit includes an encoder that converts thermometer codes to binary.

The Coarse Loop consists of two 4-stage delay chains with delays (τ_{1_c}, τ_{2_c}), where the delay of the stop path (τ_{2_c}) is controlled by a 4-bit coarse delay control code (CDCC). The 1-bit resolution of the Coarse Loop (τ_{1_c} − τ_{2_c}) is approximately nine times larger than that of the Fine Loop. It is trimmed on a per-die basis to ensure gain matching with the Fine Loop, thereby preventing code discontinuity. Details are discussed later in Section III.

During Coarse Loop operation, the CDCC is fixed to its maximum value (i.e., 1111), while the coarse-loop detector processes the time difference and generates thermometer codes representing the interval between the start and stop signals. These codes configure the CDCC values used in Fine Loop operation. The Fine Loop employs two 8-stage delay chains with delays (τ_{1_f}, τ_{2_f}), designed to achieve precise resolution suitable for high-speed memory interface calibration.

Fig. 2(b) illustrates the timing diagram of the proposed TDC and explicitly marks the Coarse-to-Fine handover for clarity. The central vertical dashed line marks the instant when the MUX selects the Fine Loop and the Coarse Loop thermometer code is translated into the CDCC value used in the Fine Loop (e.g., 1111 to 0111). The label T_fine indicates the residual interval resolved by the Fine Loop.

If the start and stop signals reverse phase at the fourth stage during Coarse Loop operation, Fine Loop adjusts the timing difference T_fine using the τ_{1_f} − τ_{2_f} time resolution defined by the CDCC. The Fine Loop enable signal (fl_en) toggles when start_c and stop_c transition from high to low, marking the completion of the Coarse Loop and enabling the Fine Loop. After Fine Loop operation, the final Coarse and Fine Loop codes are encoded into a binary output, completing the TDC operation.

Fig. 2. Illustration of the proposed two-step TDC (a) block diagram and (b) timing diagram.

1. Phase Detector with Hold-Time Metastability Mitigation

Fig. 3(a) illustrates the proposed phase detector based on a TSPC sampling structure, which includes a charge elimination circuit to resolve hold-time metastability. The circuit senses transitions using internal node capacitance, making it suitable for high-speed, low-power applications. While the conventional TSPC structure provides stable setup-time behavior, as illustrated in the setup-time waveform of Fig. 3(b), it inherently suffers from hold-time metastability, as shown in the hold-time waveform of the same figure.

When the rising edge of the start signal occurs before the stop signal, node n1 transitions from high to low with a rate of Δ₁, followed by n2 transitioning at Δs (Δ₁ > Δs). This ensures that n1 reaches threshold earlier, allowing n2 to remain above Vth and maintain a high output. Conversely, when the stop signal precedes the start signal, n2 transitions first at Δh₁. If the timing difference between signals is small, the falling edge of n1 interferes with n2, reducing its rate to Δh₂ and causing n2 to remain above threshold, resulting in a hold-time violation.

Fig. 3. Proposed TSPC-based phase detector with (a) circuit including charge elimination for hold-time mitigation and (b) waveforms illustrating metastability and its suppression.

To address this issue, the charge elimination circuit is added at n2, as shown in Fig. 3(a), enabling faster discharge during hold-time violations. When the stop signal leads, transistor M11 activates the discharge path, increasing the transition rate of n2 to Δh'₁ and mitigating metastability. Conversely, when the start signal precedes the stop signal, M10 deactivates the discharge path, preserving the original TSPC behavior.

Unlike upsizing M4 and M5, which reduces the transition slope at n1 and degrades setup-time performance, the proposed approach improves hold-time robustness without impacting setup timing. Although the circuit cannot store arbitrary data like a conventional flip-flop, it operates reliably in the proposed TDC, which only relies on input rising edges.

Fig. 4 shows the Monte Carlo simulation results that assess the metastability performance of the proposed phase detector. The simulation sweeps the start-stop offset and evaluates the accuracy of output Q in Fig. 3(a), verifying it generates a logic high when the offset is positive and a logic low when it is negative. The results confirm that the proposed phase detector achieves metastability window below ±1 ps.

Fig. 4. Monte Carlo Simulation of the proposed phase detector.

Fig. 5 shows the simulated transfer characteristics of the conventional TSPC and the proposed TSPC with the charge elimination circuit under typical, slow, and fast process corners as well as extended voltage (1.6-2.0 V) and temperature (−40 ◦C to 125 ◦C) conditions. Results are obtained using the same start-stop offset sweep and the output transition point is monitored. An ideal phase detector would switch at 0 ps. A negative transition point corresponds to a hold-time violation, while a positive transition indicates a setup-time violation.

In the conventional structure, the transition occurs at −37 ps, −24 ps, and −18 ps for the slow, typical, and fast corners, indicating large hold-time variation. By contrast, the proposed structure shows a hold-time violation of only −4 ps at the slow corner, an exact 0 ps transition under typical conditions, and a small setup-time violation of +3 ps at the fast corner.

This behavior can be explained by the additional discharge path provided by the charge elimination circuit, which accelerates the removal of residual charge at n2 and suppresses hold-time failures. When the start and stop edges are extremely close, however, the propagation delay of the first inverter may cause n2 to discharge slightly before stabilization, resulting in a minor setup-time degradation at the fast corner. Nevertheless, this small shift is far less severe than the large hold-time violations of the conventional structure, confirming that the proposed phase detector achieves much more robust operation across extreme PVT conditions.

Fig. 5. Simulated transfer characteristics of the conventional and proposed TSPC phase detectors under extended PVT conditions.

2. Delay Chain Optimization Based on Twist Power-gating (TPG) Technique

In multi-die packaging environments, high-capacity memory systems require strict control of standby current. To meet these requirements, NAND Flash adopts multi-GOX designs to ensure reliability and applies power-gating in high-speed regions to manage standby current ^[11]. The proposed TDC determines its maximum sampling speed based on the critical timing path, where the phase detector must output results between the rising and falling edges of the start signal to ensure stable sampling. Assuming a 50% duty cycle, stable operation at 100 MS/s requires the following condition:

Due to NAND process characteristics, standard devices exhibit propagation delays exceeding 200 ps, requiring high-speed transistors in the delay chain to meet timing constraints. To suppress leakage from these transistors, a power-gating scheme employing high-Vth switches is applied. Conventional power-gating, as shown in Fig. 6(a), requires large switches to avoid performance degradation during normal operation.

Fig. 6. Illustration of delay chains with (a) conventional and (b) TPG schemes.

The proposed TPG structure in Fig. 6(b) reduces switch size by isolating the main signal path from control transistors. Signal quality depends on transition direction. During rising transitions, M1 and M4 actively drive the n1 and Out nodes, while stacked transistors such as M2 and S2 or M3 and S1 are turning off. This enables fast timing comparisons along non-stacked paths, reducing power-gating impact. As shown in Fig. 2(b), the TDC compares the rising edges of the start and stop signals, while falling edges are used only to reset internal nodes.

During falling transitions, the signal passes through stacked transistors, causing degradation. However, since this phase does not affect comparison, such degradation is tolerable. This asymmetry allows smaller switches, reducing leakage and area. When the TDC is disabled, holding the input high ensures that M1 and M4 maintain valid node levels, while the high-Vth switches S1 and S2 remain off, effectively suppressing leakage current.

Fig. 7 compares the propagation delay of the conventional and proposed schemes with respect to switch size. The proposed TPG scheme shows only 2.13% delay degradation over the no power-gating case and still outperforms the conventional design with a switch four times larger than default.

Fig. 7. Propagation delay comparison based on power-gating switch configurations.

Fig. 8 shows the Coarse Loop delay chain, which uses stacked inverters with the TPG structure. Fig. 8(a) shows the start path unit, while Fig. 8(b) presents the stop path unit with programmable delay control using CDCC. When CDCC is high, additional stacked transistors in the stop path are activated, reducing its delay relative to the start path. When CDCC is low, only the base path is active, resulting in a delay matched to the start path.

The number of stacked transistors controlled by CDCC in Fig. 8(b) is trimmed per die to keep the Coarse Loop resolution approximately nine times that of the Fine Loop, preventing code discontinuity and compensating for pro-cess variations. The Fine Loop delay chain adopts the structure in Fig. 6(b), with gate lengths of the start and stop paths adjusted to generate the desired delays τ_{1_f} and τ_{2_f}.

Fig. 8. Illustration of the proposed Coarse Loop delay chain units showing (a) start path unit and (b) stop path unit.