I. INTRODUCTION

Epilepsy is a brain disease characterized by recurrent seizures due to transient over-excitation of brain nerve cells, representing the second most common chronic neurological disorder after headache disorders. Electrical brain stimulation has emerged as a critical therapeutic intervention for medication-resistant seizure therapy, with recent clinical studies demonstrating significant efficacy ^[1,2]. These clinical outcomes establish electrical stimulation as a vital treatment option for refractory epilepsy patients.

In electrical current stimulators, when bi-phasic current is injected from the working electrode to the reference electrode, the voltage level of the working electrode fluctuates according to electrode-tissue impedance variations. Therefore, high compliance voltage is essential to deliver adequate charge to tissue regardless of stimulation current amplitude. Recent advances in high-voltage neural stimulators have demonstrated impressive capabilities, with ^[3] achieving 30V compliance voltage in an 8-channel system using 180 nm BCD CMOS technology, maintaining single-cycle charge imbalance of only 0.77% with 98% output power efficiency. Additionally, 32-channel independently programmable stimulators have been developed with ±22.5 V compliance voltage and current resolution ranging from 4.31 µA/bit to 48 µA/bit, supporting stimulation currents from 0-12.24 mA ^[4]. However, these high-voltage approaches typically require specialized high-voltage CMOS processes, resulting in significant disadvantages in power consumption, chip area, and manufacturing cost.

The injection of stimulation current causes residual charge accumulation at the electrode-electrolyte interface, creating DC current flow that can damage nerve tissue and corrode electrodes, necessitating charge balancing functionality for safety. Active charge balancing can achieve faster convergence than passive methods. Recent techniques ^[5] further attempt to break the trade-off between accuracy and balancing time, and some designs also utilize digital logic to determine the termination of the balancing process ^[6]. While active charge balancing schemes can remove residual charge without additional long discharging periods enabling fast stimulation frequency, passive charge balancing schemes offer advantages in circuit complexity, power consumption, and area efficiency ^[7,8]. Given that electrical stimulation for seizure suppression is effective at low stimulation frequencies of 5 Hz ^[9], and recent studies have shown that 1 Hz low-frequency stimulation can achieve nearly complete seizure suppression in the hippocampus ^[10,11], passive charge balancing schemes that minimize time constants associated with switch resistance and electrode-tissue interface impedance present a feasible alternative to active schemes.

This work proposes a 64-channel neural stimulator integrated circuit (IC) for seizure suppression applications. The proposed design addresses key challenges in neural stimulation—such as limited compliance voltage, inefficient area utilization, and slow passive charge balancing—through three circuit techniques.

First, we maximize the compliance voltage using a regulated cascode output stage, which maintains high output impedance and accurate current regulation even under low-voltage operation, enabling up to 98% of VDD compliance in standard 0.18 µm CMOS technology.

Second, we introduce a 8 + 3-bit DAC architecture that achieves high current resolution with minimal area overhead. Compared to prior single-DAC designs ^[7,8], this structure enables finer channel-per-resolution and improved scalability in multi-channel applications.

Third, a bootstrapped switch with ultra-low on resistance is employed in the passive charge balancing path. This reduces the switch's Ron from 43.48 Ω to 19.56 Ω, significantly shortening the discharge time. Given that the safe limit of residual charge to prevent tissue damage and electrode corrosion is 15 nC ^[12], this improvement is crucial to ensure safety and compliance.

The proposed system achieves 98% supply voltage efficiency (4.9 V from 5 V supply) while maintaining residual charge below 1 nC within safety limits at 5 Hz stimulation frequency. Importantly, this work demonstrates seizure suppression effectiveness through comprehensive in-vivo verification in animal tests, validating both the technical performance and clinical feasibility of the proposed 64-channel stimulator system.

II. PROPOSED SYSTEM DESIGN

Fig. 1 shows the architecture of the proposed 64-channel neural stimulator system designed to address the key challenges identified in current neural stimulation technology: achieving high compliance voltage in standard CMOS processes, maintaining precise charge balancing with minimal residual charge, and providing independent multi-channel control for effective seizure suppression. The overall system consists of a global 8-bit current digital-to-analog converter (DAC), level shifter, bandgap reference, digital controller, and 64 independent stimulator units, each comprising an output current driver with local 3-bit DAC and bootstrapped switch for charge balancing, as shown in Fig. 1. For example, to activate the first channel, set CH1 = High, Amp_p1 = High, and Amp_n1 = High, and enable 1× amplification through a current mirror via a switch with a built-in AND gate.

Fig. 1. Block diagram of proposed stimulator IC.

The hierarchical current control architecture enables precise stimulation parameter adjustment across a wide dynamic range. The global 8-bit DAC combined with local 3-bit DACs provides fine-grained current control from 1 µA to 1.8 mA, offering superior resolution compared to existing single DAC systems ^[7,8] while maintaining compact area per channel. This dual-DAC approach allows for both coarse global adjustment and fine local trimming, essential for the heterogeneous impedance characteristics encountered in multi-channel neural interfaces.

The output driver implemented with a regulated cascode current source generates bi-phasic pulses with an almost complete VDD compliance range, achieving 4.9 V from a 5 V supply (98% efficiency) by setting Vrefp to 4.98 V and Vrefn to 0.02 V, respectively. This represents a significant advancement over conventional approaches that typically require high-voltage processes to achieve comparable compliance voltages ^[3,4]. The regulated cascode topology maintains constant current injection regardless of voltage fluctuations across the electrode-tissue impedance, enabling reliable stimulation delivery across varying tissue conditions.

The stimulation current pulse is configured with a comprehensive four-phase sequence: anodic/cathodic, off period, cathodic/anodic, and discharge periods, as illustrated in the timing diagram of Fig. 2. This configuration supports mono-phasic, symmetric, and asymmetric bi-phasic stimuli, providing the flexibility required for diverse neural stimulation protocols. The pulse width is programmable from 1 µs to 1023 µs, accommodating the range typically used in seizure suppression applications where precise temporal control is essential for therapeutic efficacy. The SPI_MOSI command signal triggers the stimulation, enabling real-time control and synchronization with external seizure detection algorithms.

Fig. 2. Timing diagram of stimulation current with SPI interface.

The digital controller operates through an SPI slave interface at 10 MHz, enabling real-time configuration of stimulation parameters including C_H (channel activation), Ton (timing information for anodic, off, cathodic, and discharge pulses), DAC (global current setting), and Amp (local current adjustment). This high-speed interface ensures rapid parameter updates necessary for responsive stimulation protocols, where stimulation parameters may need adjustment based on real-time seizure detection algorithms. The level shifter changes the DC level of digital signals from the digital controller (1.8 V) to the high voltage level required for the output current driver (5V), enabling efficient dual-supply operation that minimizes overall power consumption.

Fig. 3 shows the schematic of the regulated cascode output current driver, which represents the core innovation enabling high compliance voltage operation in standard 0.18 µm CMOS technology. In this topology, the impedance of the output node is significantly boosted via a regulated cascode structure. This allows for constant current injection independent of voltage fluctuations across the electrode-tissue interface, even over a wide range of current amplitudes. The key to achieving high compliance lies in the negative feedback loop formed by operational transconductance amplifiers (OTAs), which maintains the drain voltages of current source MOSFET near fixed reference levels—Vrefp = 4.98 V and Vrefn = 0.02 V—close to the supply rails. Although the current source transistors operate in the triode region, their drain voltages are tightly regulated. As a result, accurate current mirroring is preserved, and device reliability is maintained because the drain-source voltage remains stable and the current remains within safe operating limits. Additionally, the gm-boosting effect of the OTA and negative feedback increases the effective output impedance, compensating for the reduced intrinsic resistance of triode-region transistors. This configuration enables a compliance voltage of 4.9 V from a 5 V supply, achieving 98% VDD utilization efficiency, which exceeds conventional cascode designs that typically achieve 80-95% compliance in prior literature ^[3,4]. Furthermore, the current amplitude of biphasic anodic and cathodic pulses is finely adjusted using a 3-bit local DAC, which scales the current generated by the 8-bit global DAC, enabling channel-level current optimization with high resolution and area efficiency.

Fig. 3. Schematic of regulated cascode output current driver achieving 4.9 V compliance voltage from 5 V supply.

Fig. 4(a) shows the schematic of the bootstrapped switch designed for passive charge balancing, which addresses the critical safety requirement of minimizing residual charge accumulation. In switch-based passive charge balancing to eliminate residual charge by shorting the working and reference electrodes, the time constant directly related to the required discharging time is determined by the electrode-tissue impedance and the resistance of the switch. Therefore, a bootstrapped switch is employed instead of a conventional transmission gate switch to achieve faster passive charge balancing with reduced discharge time.

Fig. 4. (a) Schematic of bootstrapped switch for charge balancing with reduced on-resistance of 19.56 Ω. (b) Step of Φ = High (c) Step of Φ = Low.

The operating principle of the bootstrapped switch is illustrated in Figs. 4(b) and 4(c). When the clock signal Φ is high, the drain-source node of M3 is connected to ground, storing the common-mode voltage (Vcm) across the MOS capacitor. In the Φ-low phase, this stored charge is shifted upward, boosting the gate voltage of M6 to approximately Vcm + VDD. As a result, the gate-source voltage of M6 is maximized and its on-resistance is minimized. Series transistors M2 and M7 protect M1 and M8 from overvoltage stress during this operation, ensuring device reliability.

The on-resistance of the bootstrapped switch is reduced to 19.56 Ω from the 43.48 Ω of conventional switches, representing a 55% reduction that significantly improves the discharge time constant. This improvement is particularly important for maintaining safe operation within the 15 nC residual charge limit established for neural stimulation safety ^[12]. Assuming a discharging period of 8.9 µs with 100 µA current stimulation, the proposed passive charge balancing scheme guarantees residual charge of less than 1 nC, which is 20 times lower than the established safety limit.

To support this claim quantitatively, we analyzed the discharge profile in two stages: an initial linear discharge dominated by voltage division between Rs and Ron, followed by an exponential decay governed by the RC time constant. Due to the lower Ron of the bootstrapped switch, the initial voltage after linear drop becomes smaller, resulting in a lower starting point for the exponential discharge phase. Furthermore, the RC time constant τ = (Rs + Ron) · C_H decreases from 1004.35 µs to 1001.95 µs. Although the difference in τ appears small, the discharge time to reach 1 nC of residual charge (approximately 3.69τ) is shortened by 8.9 µs, as shown in our simulation. This two-fold effect—lower initial voltage and reduced time constant—leads to faster passive charge balancing, ensuring safety under the 15 nC limit.

III. MEASUREMENT RESULTS

The proposed electrical stimulator IC is fabricated in a 0.18 µm standard CMOS process, demonstrating the cost effectiveness and manufacturing compatibility of the design approach. Fig. 5 shows the chip micrograph of the stimulator IC. The active area of the single-channel stimulator units, array is 987.6 µm × 815.7 µm (0.805 mm²), while the digital controller occupies 1.4 mm × 1.4 mm. The efficient layout design and shared digital controller architecture result in an effective area utilization of 0.0125 mm² per channel for the complete 64-channel system, enabling compact implementation suitable for implantable applications.

Fig. 5. Chip micrograph of fabricated stimulator IC in 0.18 µm CMOS process.

Fig. 6 shows the measured compliance voltage with respect to output current amplitude from 10 µA to 500 µA when different reference voltages are applied. The reference voltages Vrefp and Vrefn in Fig. 3 are tested with settings of 4.8 V/0.2 V, 4.9 V/0.1 V, 4.95 V/0.05 V, and 4.98 V/0.02 V to evaluate the compliance voltage performance across varying operating conditions. The maximum compliance voltage of 4.9 V is achieved with Vrefp and Vrefn of 4.98 V and 0.02V at the output current of 10 µA, demonstrating the effectiveness of the regulated cascode approach in maximizing voltage utilization. At the output current of 50 µA utilized in the in-vivo test, the stimulator maintains a high compliance voltage of 4.75 V, ensuring adequate drive capability for effective tissue stimulation across the range of electrode-tissue impedances encountered in practice.

Fig. 6. Measured compliance voltage according to the output current for different reference voltage settings.

The measured compliance voltage performance validates the design approach of maximizing VDD utilization in standard CMOS technology, achieving 98% efficiency that exceeds recent high-voltage implementations requiring specialized processes. This result demonstrates that effective neural stimulation can be achieved without resorting to expensive high-voltage fabrication technologies, significantly reducing manufacturing costs while maintaining therapeutic efficacy.

Fig. 7 compares the required discharge times of the conventional transmission gate switch and the proposed bootstrapped switch when a monophasic stimulation pulse is applied. The evaluation uses an equivalent circuit model of the electrode-electrolyte interface with C_H = 100 nF, R_F = 10 MΩ, and R_S = 10 kΩ as established in literature ^[13]. The monophasic pulse is programmed with an amplitude of 400 µA and a duration of 150 µs, as shown in Fig. 7(a), representing typical parameters used in seizure suppression applications.

Fig. 7. Comparison of discharge time between conventional switch (86.9 µs) and bootstrapped switch (53.4 µs). (a) Monophasic stimulation pulse. (b) Conventional switch response. (c) Bootstrapped switch response.

Figs. 7(b) and 7(c) show the measured voltage across C_H when conventional and bootstrapped switches are used, respectively. The discharge time required to reduce residual charge below 1 nC is 86.9 µs for the conventional switch, whereas the bootstrapped switch achieves it in 53.4 µs, representing a 39% improvement in discharge speed. This measurement is conducted under the condition that timing is measured from the start of charge balancing until the residual charge reaches 1 nC, demonstrating the superior performance of the bootstrapped switch design in maintaining safe charge levels.

The improved discharge performance directly translates to enhanced safety margins and enables more frequent stimulation protocols when required. The faster discharge also reduces the risk of charge accumulation over multiple stimulation cycles, which is particularly important for long-term implantable applications where consistent performance over months to years is essential.

Fig. 8 shows the measured voltage between working and reference electrodes during continuous operation at 5 Hz stimulation frequency with bi-phasic current pulses of 100 µA amplitude and 100 µs pulse width. The total stimulation duration is 30 seconds, with Fig. 8(a) showing the waveform for 10 seconds in the latter half of the stimulation period, and Fig. 8(b) providing a zoomed view of 2 seconds during steady-state operation. The voltage fluctuation generated by residual charges is at most 7.5 mV as shown in Fig. 8(b), which corresponds to an equivalent residual charge of 0.75 nC. This measured residual charge of 0.75 nC is 20 times lower than the established safety limit of 15 nC ^[12], demonstrating substantial safety margins that ensure long-term biocompatibility and electrode stability. The consistent low residual charge across extended stimulation periods validates the effectiveness of the passive charge balancing approach for seizure suppression applications, where reliable long-term operation is critical for therapeutic success.

Fig. 8. Measured residual voltage at 5 Hz stimulation frequency with 100 µA biphasic pulses. (a) 10-second waveform. (b) Zoomed 2-second view showing 7.5 mV maximum fluctuation.

IV. IN-VIVO TEST

In-vivo animal experiments in rats were performed to verify the efficacy of the proposed stimulator for seizure suppression applications, providing critical validation of the system's therapeutic potential. Fig. 9(a) shows the experimental environment for the test. The PC updates stimulation parameters to the FPGA through the UART interface, followed by SPI communication from FPGA to the stimulation IC, enabling real-time control of stimulation protocols. While stimulation pulses are applied to the rat, the commercial RHS recording platform from Intan Technologies records the ECoG signals, which are transmitted to the PC for real-time monitoring and analysis.

Fig. 9. Measurement setup for animal test. (a) Complete experimental environment. (b) Graphene electrode placement on rat cortical areas.

As shown in Fig. 9(b), a micro-fabricated graphene electrode, selected for its low impedance and biocompatibility, is directly attached to the somatosensory and/or motor cortical areas of the brain for the experiment. The graphene electrode demonstrates favorable impedance characteristics as shown in Fig. 10, with impedance values appropriate for effective current injection while maintaining low polarization effects that could interfere with stimulation delivery or recording quality.

Fig. 10. Impedance characteristics of micro-fabricated graphene electrode used in in-vivo experiments.

Bicuculline is used to induce seizure-like activity and is injected into the brain's somatosensory and motor cortex at a concentration of 15 mM, creating a reliable and reproducible epilepsy model for testing stimulation efficacy. This pharmacological seizure model provides consistent seizure patterns that enable systematic evaluation of stimulation parameters and their therapeutic effects.

Fig. 11(a) shows the complete ECoG waveform of bicuculline-induced seizure activity and its suppression through electrical stimulation. The stimulation is performed at 5 Hz frequency, which has been demonstrated as most effective for seizure inhibition in both clinical studies ^[1,2] and preclinical research ^[9,10]. Stimulation is continued for 40 seconds with current amplitude of 50 µA and pulse width of 10 µs, parameters selected based on safety considerations and previous efficacy studies.

Figs. 11(b)-11(e) shows detailed waveforms corresponding to different phases of the experiment: seizure onset, active stimulation period, transition period from seizure cessation, and complete suppression, respectively. The progression clearly demonstrates the therapeutic effect of the electrical stimulation in suppressing seizure activity. After 40 seconds of stimulation, seizure suppression is achieved within 14 seconds, demonstrating rapid therapeutic response consistent with clinical observations of electrical brain stimulation for epilepsy treatment.

Fig. 11. Experimental results of seizure suppression in bicuculline-induced epilepsy model. (a) Complete ECoG waveform. (b)-(e) Detailed phases: seizure onset, stimulation, transition, and suppression.

The successful in-vivo validation confirms that the proposed 64-channel stimulator system can deliver therapeutically effective stimulation while maintaining the sub-nC charge balancing performance demonstrated in bench testing. The 50 µA stimulation amplitude used in the animal studies falls well within the 1 µA to 1.8 mA range of the system, with the 4.75 V compliance voltage at this current level providing adequate drive capability for effective tissue stimulation.

The seizure suppression achieved with 5 Hz stimulation validates the design choice of optimizing the passive charge balancing for low-frequency applications, as this stimulation frequency provides sufficient time between pulses for complete charge discharge while maintaining therapeutic efficacy.

The rapid seizure suppression (14 seconds after stimulation cessation) demonstrates the potential for responsive stimulation protocols where stimulation can be applied on-demand based on seizure detection, minimizing unnecessary stimulation and extending battery life in implantable applications. These in-vivo results, combined with the measured electrical performance, demonstrate that the proposed system successfully addresses the key requirements for practical neural stimulation: high compliance voltage for effective stimulation delivery, precise charge balancing for safety, multichannel capability for spatial control, and therapeutic efficacy in seizure suppression applications.

V. CONCLUSION

We have presented a 64-channel implantable current-mode stimulator IC with passive charge balancing for seizure suppression applications. The proposed system achieves 98% VDD utilization efficiency (4.9 V from 5 V supply) using standard 0.18 µm CMOS technology, eliminating the need for expensive high-voltage processes while exceeding typical performance of 80-95% reported in literature.

The passive charge balancing with bootstrapped switch reduces on-resistance by 55% and maintains residual charge below 1nC—20 times better than the established 15nC safety limit. The 64-channel architecture provides the current neural stimulators with superior area efficiency of 0.0125 mm² per channel. In-vivo validation demonstrates effective seizure suppression within 14 seconds using 5 Hz stimulation, confirming the therapeutic efficacy for drug-resistant epilepsy treatment. The combination of high channel count (64), optimal VDD utilization (98%), enhanced safety (20× better than limit), cost-effective standard CMOS implementation, and in-vivo validation makes this system a promising solution for next-generation implantable neural stimulation devices.