I. INTRODUCTION

The use of delta-sigma ($\Delta\Sigma$) modulators that incorporate noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADC) as quantizers has been explored for the purpose of achieving higher-order noise shaping (NS) ^[1]. Hybrid noise coupling, integrating analog and digital feedback, enhances NS. However, this approach discards the fine quantizer after using it only for increasing NS order, thus presenting an inefficiency ^[2]. Achieving high precision demands a high-resolution quantizer and digital-to-analog converter (DAC). Digital processing techniques have been explored to relax this requirement, but their effectiveness is constrained by analog--digital mismatches, resulting in noise leakages ^[3,4].

This work presents a hybrid $\Delta\Sigma$ modulator that uses a 6-bit SAR quantizer with 1-bit redundancy to enhance second-order NS while improving noise suppression by reusing the fine quantizer.

This paper details the system architecture, circuit implementation, and simulation results, thereby validating the noise suppression and power efficiency of the proposed solution.

II. ARCHITECTURE

Fig. 1 illustrates the proposed $\Delta\Sigma$ modulator with hybrid NS-SAR ADC and digital cancellation. It employs two cascaded integrators in the $\Delta\Sigma$ modulator loop filter, a 6-bit quantizer consisting of a 5-bit coarse and 1-bit fine ADC, a three-input comparator, and two cascaded integrators for residue integration. The cascaded integrators successively process the input signal (${U}$) along with the coarse quantizer output (${D}_{\rm Coarse}$), producing the outputs ${X}_{1}$ and ${X}_{2}$.

The input to the quantizer, represented by node ${Y}$, is obtained from ${X}_{2}$ and the digitally processed fine quantizer output (${D}_{\rm Fine}$). The digital process (${H}_{\rm D1}$) is given by $1 -(-z^{-1})^{2}$ and creates a second-order noise-transfer function (NTF) for the coarse quantization error (${E}_{\rm Coarse}$) within the loop filter.

The coarse quantizer compares ${Y}$ to the analog feedback path (${I}_{\rm AF}$), which consists of the processed fine quantizer residue ($R_{\rm Fine}$) obtained from the two cascaded integrators and eliminates $E_{\rm Fine}$ within the loop filter.

After coarse quantization, the residue ($R_{\rm Coarse}$) is obtained.

The fine quantizer performs a 1-bit conversion using the same $I_{\rm AF}$. Then, it generates $D_{\rm Fine}$ and $R_{\rm Fine}$.

Based on Eqs. (5)-(7), $D_{\rm Fine}$ consists only of coarse and fine quantization errors (QE).

Accordingly, ${Y}$ to $D_{\rm Coarse}$ is derived as follows:

Consequently, $E_{\rm Fine}$ is canceled out, while $E_{\rm Coarse}$ undergoes second-order NS. When the NS-SAR is incorporated into the $\Delta\Sigma$ modulator loop filter, the ${U}$ to $D_{\rm Coarse}$ transfer function is derived as follows:

The final modulator output ($D_{\rm Total}$) is processed through digital cancellation between $D_{\rm Coarse}$ and $D_{\rm Fine}$ multiplied by $H_{\rm D2}$, which is given by ($1-z^{-1})^{4}$.

Consequently, the NTF of $D_{\rm Total}$ contains only $E_{\rm Fine}$, indicating that the total quantizer is fully utilized. Thus, the noise floor is further lowered compared to that of the coarse quantizer alone. Notably, the proposed architecture inherently achieves a fourth-order NTF response to $E_{\rm Coarse}$, as shown in Eq. (11). Assuming a mismatch factor $\Delta$ between the analog and digital filters, the leakage due to imperfect digital cancellation from $D_{\rm Coarse}+{H}_{\rm D2} \cdot D_{\rm Fine}$ is derived as follows:

The leakage term originating from a mismatch in $E_{\rm Coarse}$ is also shaped by the fourth-order NTF owing to the inherent loop filter. Since $\Delta$ is a small mismatch factor, the resulting noise floor from leakage is significantly lower than that of $E_{\rm Fine}$. Consequently, the effect of $E_{\rm Coarse}$ leakage is substantially suppressed.

Fig. 1. Proposed $\Delta\Sigma$ modulator structure using hybrid NS-SAR with digital cancellation.

III. CIRCUIT DESCRIPTION

As illustrated in Fig. 2, the proposed circuit consists of a switched capacitor (SC) integrator, a 7-bit nonbinary-weighted capacitor array, two SC arrays, a three-input dynamic comparator, a digital decoder for multiplication with $H_{\rm D1}$ and asynchronous SAR clock generation, nonbinary to binary decoder, two cascaded gm-C integrators, and an $H_{\rm D2}$ multiplier block.

The clock operates in two main phases, ${\Phi}_{\rm ODD}$ and $\Phi_{\rm EVEN}$, where each phase corresponds to one conversion period. Each phase is further divided into $\Phi_{1}$ and $\Phi_{2}$, resulting in a four-phase operation ^[2]. The SC integrator is the core component of the $\Delta\Sigma$ modulator loop filter. An additional switch allows the reuse of a single SC integrator, enabling amplifier sharing ^[5]. The 7-bit SAR quantizer employs a 7-bit nonbinary-weighted capacitor array for 1-bit redundancy ^[6].

During $\Phi_{1}$ of $\Phi_{\rm ODD}$, the first stage samples ${U}$ on ${C}_{\rm S1}$, and the second-stage integration is performed by connecting $C_{\rm F2}$ to the amplifier input through SW${}_{\rm I2}$ while opening SW${}_{\rm I1}$. At this time, the bottom plate of $C_{\rm S2}$ is connected to the reference controlled by $D_{\rm Coarse}$. When $X_{2}$ is sampled on the top plate of the total DAC array with $72{\cdot }C_{\rm SAR}$, where $C_{\rm SAR}$ is the unit capacitance of the SAR quantizer, the bottom plate is connected to the reference selected by $D_{\rm Fine}$ and multiplied by $H_{\rm D1}$. The stored charge on $C_{\rm EVEN}$ at $\Phi_{1}$ of $\Phi_{\rm EVEN}$ is coupled to the input of two successively cascaded gm-C integrators for integration.

At the start of $\Phi_{2}$ in $\Phi_{\rm ODD}$, the bottom plate of $C_{\rm S1}$ is connected to the reference controlled by $D_{\rm Coarse}$. Then, the stored ${U}$ is transferred to $C_{\rm F1}$ through the SC integrator, where SW${}_{\rm I1}$ is closed while SW${}_{\rm I2}$ is opened. Each $C_{\rm I1}$ and $C_{\rm I2}$ is disconnected from its respective gm-${C}$ integrator output and then referenced by the three-input comparator ^[7].

During $\Phi_{2}$ in $\Phi_{\rm ODD}$, the SAR quantization digital outputs are decoded from nonbinary to binary, and the resulting 6-bit output is separated into $D_{\rm Coarse}$ and $D_{\rm Fine}$ for use in digital error feedback and digital cancellation, respectively. No additional processing is required between the coarse and fine quantization steps during SAR conversion ^[6,8]. Furthermore, no extra clock cycles or timing constraints are introduced as the full 7-bit conversion is executed sequentially without interruption. After the SAR conversion, the digital cancellation is performed, where $D_{\rm Coarse}$ is combined with $D_{\rm Fine}$ multiplied by $H_{\rm D2}$, yielding the final output $D_{\rm Total}$.

The operation in $\Phi_{\rm EVEN}$ is identical to that in $\Phi_{\rm ODD}$, except that a ping-pong operation is employed, where $C_{\rm ODD}$ and $C_{\rm EVEN}$ alternately store the charge during $\Phi_{\rm ODD}$ and $\Phi_{\rm EVEN}$, respectively, to be used in the opposite phase ^[2].

The proposed architecture offers several key architectural choices that simultaneously reduce circuit complexity and power consumption. First, amplifier sharing in the SC integrator with phase interleaving reduces the number of required amplifiers, directly lowering analog power consumption. Second, although the proposed architecture achieves the same SQNR performance as conventional fourth-order NTF modulators with four cascaded SC integrators (CIFB/CIFF), digital cancellation enables a one-bit reduction in feedback DAC resolution; this reduction enables the use of larger thermometer unit capacitors in the feedback DAC for the same total sampling capacitance, thereby improving capacitor mismatch characteristics. The complexity of the control logic for dynamic element matching circuits, such as DWA, is also reduced by half, further enhancing power efficiency. Third, the proposed architecture eliminates the need for a feedback DAC array in the third and fourth SC integrator stages, which removes routing overhead and further simplifies circuit complexity. Compared to the CIFF architecture, no additional adder amplifier is required at the quantizer input for signal summing, which also contributes to lower power and complexity. In addition, the third and fourth stages of a conventional $\Delta\Sigma$ are replaced by open-loop gm-C integrators, which consume less power than SC integrators and do not require feedback DACs or their associated routing. This open-loop structure, together with the small signal swing achieved by cascaded integration of the $R_{\rm Fine}$ signal, greatly reduces the impact of gm-C integrator gain nonlinearity and allows for significant static current reduction. Finally, unlike conventional $\Delta\Sigma$ modulators using NS-SAR quantizers that employ a $D_{\rm Coarse}$ and a digital filter, where the architecture is constrained by processing time and suffers from reduced input signal swing due to residue saturation, the proposed architecture utilizes only a 1-bit $D_{\rm FINE}$ for both $H_{\rm D1}$ and $H_{\rm D2}$ digital filters. Since $H_{\rm D1}$ ($=1-(1-z^{-1})^2$) consists of both the original and a second-order noise-shaped signal, the resulting swing remains significantly smaller; this results in an increased dynamic range (DR) at the quantizer input, reduced digital logic complexity, and relaxed timing constraints. By combining these strategies, the proposed architecture achieves a reduction in circuit complexity and lower power consumption, all while maintaining high conversion performance.

Fig. 2. Circuit implementation of proposed $\Delta\Sigma$ modulator.

IV. SIMULATION RESULTS

The proposed $\Delta\Sigma$ modulator was designed and validated via circuit-level simulations based on a 0.18-$\mu$m 1P6M standard complementary metal-oxide-semiconductor (CMOS) process.

Capacitor mismatch in standalone NS-SAR ADCs directly limits SNDR, INL, and DNL because mismatch errors propagate to the output without NS. Conventional digital error correction cannot compensate for this limitation since DAC mismatch directly impacts residue generation. Calibration circuits can alleviate mismatch effects, but they increase circuit complexity and power consumption. Mismatch Error Shaping (MES) is widely adopted to suppress DAC mismatch as it shapes mismatch errors out of band and introduces a dithering effect that suppresses deterministic in-band tones, enabling high SNDR ^[9,10]. However, despite its benefits, MES introduces additional circuit complexity and reduces DR. In NS-SAR $\Delta\Sigma$ modulators, the main loop filter inherently shapes most non-periodic DAC mismatch errors out of the band, often eliminating the need for additional calibration ^[1,2]. Nevertheless, in the absence of MES, static mismatch components can still introduce in-band tones, which must be carefully verified.

Monte-Carlo simulations were conducted by sweeping the capacitor mismatch from 0\% to 1.5\%, with 200 iterations at each point. As illustrated in Fig. 3, the SNDR degradation remains within 6 dB for up to 0.63\% mismatch. In this work, a total thermal noise target of 96 dB is specified for an oversampling ratio of 16, ensuring that thermal noise remains the dominant noise source. Accordingly, the SNDR target limited by DAC mismatch is chosen as 102 dB; this target is compatible with the minimum capacitor matching achievable in this process but provides a limited design margin, thus requiring careful layout and routing. The unit capacitance of the NS-SAR quantizer is slightly increased to provide additional headroom. Further improvement in SNDR by decreasing DAC mismatch noise would require even larger capacitors, which increases both the switching power and the load for the final-stage SC integrator. Therefore, an optimal trade-off among matching, area, and power consumption must be considered in the design.

The input-referred error sources of the three-input dynamic comparator can be divided into thermal noise and transistor mismatch. The thermal noise arises from random fluctuations in the comparator's input devices and is broadband in nature. Transistor mismatch can lead to a static offset, input-dependent dynamic offset, and gain error caused by process variation and layout mismatch.

All the input-referred noise sources are located inside the $\Delta\Sigma$ modulator loop filter. The fourth-order NTF shapes these errors and significantly suppresses their in-band spectral components. Therefore, the in-band contribution of thermal noise becomes negligible compared to the shaped quantization noise, provided the device sizing meets the matching requirements for robust suppression of gain error from input transistor mismatch. Similarly, the dynamic offset caused by transistor mismatch is noise-shaped by the loop filter and further suppressed through a symmetric layout and careful sizing of the input transistors. In this architecture, the static offset is digitally corrected using the 1-bit redundancy of the NS-SAR quantizer.

However, in the proposed architecture, the multi-input comparator sums the output of the second SC integrator with the sampled $H_{\rm D1}\cdot E_{\rm Fine}$ and the analog error feedback path (${I}_{\rm AF}$) from the outputs of each cascade gm-C integrator ^[7]. This summing can cause the zero of the NTF to deviate from the unit circle. Although this effect is also suppressed by NS, it must be verified because a fourth-order NTF demands a precise transfer function. Even small coefficient deviations could lead to a substantial degradation in SQNR. As shown in Fig. 4, to verify the robustness of the proposed architecture, Monte-Carlo simulations were performed by sweeping the input transistor mismatch from 0\% to 5\%, with 200 iterations at each point. The results show that the SQNR degradation remains within 1 dB for up to 3\% mismatch, confirming that the proposed architecture is robust against input transistor mismatch in the three-input comparator.

Fig. 5 illustrates the dynamic performance for a 200-kHz input sinusoidal signal. In Fig. 5(a), the black and blue power spectral densities (PSD) represent the signal-to-quantization noise ratios (SQNR) of the discrete Fourier transforms (DFT) for $D_{\rm Coarse}$ and $D_{\rm Total}$, respectively, exhibiting the ideal performance without transient noise. For a 375-kHz bandwidth (BW) at a sampling rate of 12 MS/s and OSR = 16, the SQNR values are 102.2 dB for $D_{\rm Coarse}$ and 107.1 dB for $D_{\rm Total}$. A 5-dB improvement is observed in $D_{\rm Total}$ with digital cancellation using $D_{\rm Fine}$ due to the reduced noise floor. Fig. 5(b) presents the DFT results of $D_{\rm Coarse}$ and $D_{\rm Total}$ with transient noise simulation. In this case, the SNDRs for both are approximately 92.9 dB, as the thermal noise of the input sampling capacitor and the first-stage SC integrator dominates and exceeds the quantization noise at OSR $= 16$. However, when the OSR is reduced to 8, the SNDR values for $D_{\rm Coarse}$ and $D_{\rm Total}$ are 74.7 dB and 79.4 dB, respectively, maintaining a 5 dB improvement; this improvement is further verified by the lower NTF slope observed near the bandwidth edge. These results demonstrate that the noise floor improvement achieved by 1-bit digital cancellation becomes more pronounced as thermal noise is reduced or in wide-band applications.

The total power consumption is 1.3 mW under a 1.8-V power supply. The ADC achieves figures of merit (FoMs) of 177.5 dB, comparable to those of $\Delta\Sigma$ modulators with NS-SAR, as shown in Table 1. The reduced power consumption stems from the NS-SAR based quantizer, SC integrator sharing, and the use of digital cancellation, which collectively minimize analog complexity while maintaining state-of-the-art performance, as summarized in Table 1.

Fig. 3. Simulated SNR as a function of capacitor mismatch ($1\sigma$) in the binary-weighted DAC of the SAR quantizer at $\text{OSR} = 16$.

Fig. 4. Simulated SNR versus input transistor mismatch ($1\sigma$) in the three-input comparator at $\text{OSR} = 16$.

Fig. 5. Simulated output discrete Fourier transform (DFT) spectrum. (a) SQNR of $D_{\rm Coarse}$ (black) and $D_{\rm Total}$ (blue). (b) SNDR of $D_{\rm Coarse}$ (black) and $D_{\rm Total}$ (blue).

Table 1. Performance summary and comparison.

V. CONCLUSIONS

This work introduces a $\Delta\Sigma$ modulator with a digitally assisted hybrid NS-SAR quantizer. The ADC achieves an additional second-order NS while reusing the fine quantizer output, lowering the noise floor by 5 dB and reducing the DAC resolution. In a 180-nm CMOS process, the ADC has a total power consumption of 1.3 mW and achieves an SQNR of 107 dB and SNR of 92.9 dB.