I. INTRODUCTION

Neuromorphic computing, first proposed by C. Mead in the late 1980s, aims to emulate the structure and function of the human brain to enable efficient, parallel, and adaptive hardware-based information processing ^[1]. Recently, it has attracted much interest because it leverages in-memory and event-driven computation, unlike conventional von Neumann architectures, which suffer from memory bottleneck and high energy consumption ^[2-5]. Neuromorphic systems have thus become well-suited for edge computing and deep learning applications. The VLSI implementations of neuromorphic computing systems have gained more advantages over the past two decades ^[4,5]. However, the VLSI designs are predominantly based on CMOS technology, which is approaching the physical scaling limit ^[6,7]. Memristors, originally postulated by L. O. Chua in 1971 and later experimentally demonstrated by HP Lab in 2008, are recognized as the fourth fundamental circuit element and have emerged as promising candidates for implementing neuromorphic computing systems ^[8,9]. Owing to their ability to emulate synaptic plasticity through conductance modulation, memristors provide effective solutions for developing energy-efficient and densely integrated neuromorphic architectures ^[10-12]. Interestingly, vector-matrix multiplication and neural potential accumulation can be affectively realized using memristor crossbar, leveraging the Ohm's and Kirchhoff's laws ^[13-17]. To implement a single synapse, two memristors are utilized, these memristors can be positioned either on the same row or column of a crossbar array, or distributed across two separate arrays ^[18-21]. However, the implementation of large-scale neuromorphic computing systems using analog memristor array faces significant challenges due to various non-ideal device characteristics, including issues with writing and reading accuracy, conductance drift, and device variability ^[22,23]. In contrast, binary memristor crossbars arrays, constructed from filamentary-type memristors with two states of low resistance (LRS) and high resistance (HRS), are considered as viable structures for neuromorphic computing systems ^[24-29]. Previous studies have proposed several neuromorphic computing circuits based on binary memristor crossbar arrays for neuromorphic image recognition task. Notable examples include the complementary memristor crossbar and the twin memristor crossbar architectures, both of which employ two memristor arrays to implement the Exclusive-NOR (XNOR) function at circuit level for pattern recognition ^[27,28].

Reducing the number of memristors in neuromorphic circuits is crucial for improving both performance and practical feasibility. Previous study has proposed a single memristor crossbar circuit with bipolar inputs for neuromorphic image recognition ^[29]. This architecture is an optimized version of the memristor-based neuromorphic designs, derived from eliminating the constant term in the XNOR operation expansion used for pattern recognition. The single memristor crossbar array with bipolar inputs demonstrates significant advantages: it reduces the number of memristors by 50%, lower power consumption by 16.7% and 7.2%, improve the recognition rate by 7% and 4% under 10% of memristors defect rate, compared to the complementary and the twin architectures, respectively ^[29].

However, the efficiency of the single crossbar architecture degrades when processing input data with low density ^[30]. As the data density decreases, the maximum output column currents are significantly reduced, impairing the accuracy of the Winner-take-all circuit and ultimately degrading the overall performance of the crossbar architecture.

To address this issue, we propose a full XNOR circuit implementation based on the single memristor crossbar architecture enhanced with a column-wise constant current source. This approach mitigates the negative impacts of data density while leveraging the advantages of the single memristor architecture.

II. PROPOSED SINGLE MEMRISTOR CROSSBAR ARCHITECTURE FOR NEUROMORPHIC IMAGE RECOGNITION

1. The Single Memristor Crossbar Architecture for Neuromorphic Image Recognition

Memristor crossbar array implement pattern recognition effectively based on the XNOR operation to measure the similarity between two binary vectors. This approach is inspired by the expansion of the XNOR operation, as presented in Eq. (1).

(1)

$ Y= \overline{A\oplus M} =AM+A^{'}M^{'}\nonumber\\ =AM+A^{'}(1-M)\nonumber\\ =\left(A-A^{'}\right)M+A^{'}. $

In Eq. (1), let $A$ be the input vector and $M$ the pattern stored in the crossbar array, the number of 1s in $Y$ indicates the similarity of the input pattern $A$ and the stored pattern $M$. More generally, if $M$ is a matrix where each column represents a stored pattern, then $Y$ is a vector in which each element denotes the similarity between the input pattern and the stored patterns.

In Eq. (1), the Exclusive-NOR operation can be implemented using OR and AND operations to facilitate the execution on the complementary memristor crossbar array ^[27]. Here $A$ and $A^{'}$ represent the input vector and its inversion, while $M$ and $M^{'}$ store the pattern and its inversion, respectively. The similarity between the input pattern and the stored pattern is also represented by the term $\left(A-A^{'}\right)M$ along with a constant term $A^{'}$, as shown in Eq. (1). Since the element $A^{'}$ remains constant across all columns, removing it does not affect the identification of the column with the highest value, as conceptually illustrated in Fig. 1(a). Therefore, instead of utilizing complementary crossbar arrays, a single crossbar array can be used to identify the column storing the pattern most similar to the input pattern efficiently ^[29]. Eq. (1) can then be simplified as follows:

(2)

$ Y= \overline{A\oplus M} =AM+A^{'}M^{'}\nonumber\\ =AM+A^{'}(1-M)\nonumber\\ =\left(A-A^{'}\right)M\nonumber\\ =I.M, $

where $I=\left(A-A^{'}\right)$ represents the bipolar input vector with values of $1$ and $- 1$, derived from the subtraction of $A^{'}$ from $A$. Eq. (2) can be implemented using the AND operation between the bipolar input $I=\left(A-A^{'}\right)$ and a single memristor array $M$.

The concept of using a single crossbar array with a bipolar input for pattern recognition is illustrated in Fig. 1(b). Each pattern is stored in a single column of the array, where a memristor $M_{i,j}$ is set to either a low resistance state (LRS) or a high resistance state (HRS) to represent a bit 1 or 0, respectively. The output vector $Y=\left[\begin{array}{cccc}i_0 & i_1 & \cdots & i_{n-1} \end{array}\!\!\right]$ contains the output column currents, reflecting the similarity score between the input vector $A$ and the memristor array $M$. When the output current $i_k$ is the maximum, it indicates that the input pattern $A$ matches the pattern stored in the column $k$ of the memristor array.

The single memristor circuit with bipolar input is designed for image recognition, specifically for recognizing ten black and white images of size $32\times32$, shown in Fig. 1(c). Each $32\times32$ image is flattened into a 1024-bit vector and stored in a single column of the crossbar array. For example, the first pixel of image #0 is represented by the memristor $M_{0,0}$, $i_0$ is the current that represents the similarity between the input image and the image stored in the first column of the crossbar array. The Winner-take-all circuit compares the output column currents, identifies the maximum current $i_k$, and generate a rising pulse at the ${Output}_k$ indicating that the input pattern $A$ matches the pattern in column $k$.

As shown in Fig. 2, the Winner-take-all circuit is driven by the discharging voltages ${VC}_0$ to ${VC}_9$ ^[27,29]. The comparators $I_0$ to $I_9$ compare these voltages to the reference voltage $V_{REF}$ to find the fastest discharging one. When the voltage ${VC}_k$ drops below $V_{REF}$ the fastest, the corresponding comparator $I_k$ sets its output $D_k$ into 1, while the other outputs remain 0. The rising pulse $D_k$ is then passed through the Pulse Generator, generating a locking pulse that triggers the flip flop ${FF}_k$ to output $D_k$ to ${Output}_k$. Thus, when the ${Output}_k$ is set to 1 while all other outputs remain 0, the WTA circuit confirms that the discharging voltage ${VC}_k$ was the fastest to fall below $V_{REF}$, indicating that the input vector $A$ matches the pattern stored in the column $k$ of the single memristor array $M$.

Fig. 1. (a) The concept of removing the constant term in the operation of Exclusive-NOR for identifying the best match between the input pattern and the stored patterns, (b) the block diagram of the single memristor crossbar architecture with bipolar input and (c) the schematic for neuromorphic pattern recognition of ten images using single memristor crossbar array.

Fig. 2. The schematic of the Winner-take-all circuit indicating the fastest discharge voltage corresponding to the largest column current ^[29].

2. The Negative Impact of the Data Density to Single Crossbar Architecture

While the single memristor crossbar architecture offers advantages in terms of area efficiency, power consumption, and noise tolerance compared to the complementary and twin crossbar architectures, recent studies have identified a significant limitation related to the data density ^[30]. Specifically, variation in data density among input patterns adversely affect the architecture's performance. A decrease in data density results in a reduction of the output column currents, as illustrated in Fig. 3 ^[30]. Consequently, further optimization of the single memristor crossbar architecture is necessary to address this issue.

As shown in Fig. 3, a decrease in data density from 0.75 (images #6, #7, #8, #9), to 0.25 (images #0, #1, #2), results in a reduction of the maximum output column currents from approximately 8 mA to 3 mA. Notably, compared to the complementary crossbar architecture, the maximum output column currents at the data density of 0.25 decrease by a factor of about four ^[30]. The single memristor crossbar array with bipolar input performs effectively with high-density images. However, for images with low data density, all column currents are significantly reduced due to the diminished constant term, leading to the ineffective operation of the WTA circuit. Therefore, modifying the memristor circuit to fully implement the Exclusive-NOR operation is essential to improve the performance of the single crossbar array.

Fig. 3. The output column currents produced by the single memristor crossbar architecture were analyzed for images with varying data densities of 0.25 (images #0, #1, #2), 0.5 (images #3, #4, #5), and 0.75 (images #6, #7, #8, #9).

3. The Proposed Circuit for the Single Memristor Crossbar Architecture to Overcome the Negative Impact of Data Density

Although the omission of $A^{'}$ in Eq. (1) is mathematically valid and simplifies the XNOR operation, it negatively impacts the performance of the single memristor crossbar architecture due to its dependence on data density. The primary reason for the reduction in output column currents in the single crossbar architecture is the elimination of the constant $A^{'}$ in Eq. (2), which uniformly decreases the output column current across all columns. When the input pattern $A$ is high data-density, its inversion $A^{'}$ is low data-density, meaning it contains a low number of bit-1 values. In this scenario, the reduction in output column currents is small, allowing the single crossbar architecture to effectively perform the simplified XNOR function and identify the maximum output column current. Conversely, when the input pattern $A$ has low data density, its inversion $A^{'}$ has high data-density, meaning it contains a high level of bit-1 values. This dramatically reduces the output column currents, leading to a lower maximum output current. This causes the Winner-Take-All circuit to operate imprecisely and compromises the stability of the single crossbar architecture.

To mitigate the negative impact of data density, the parameter $A^{'}$ must be incorporated into all output column currents of the single crossbar architecture. This adjustment stabilizes the output column currents, particularly when data density decreases.

In this work, we propose a full Exclusive-NOR function for the single memristor crossbar architecture by introducing a column-wise constant term. The full Exclusive-NOR operation is represented as follows:

(3)

$ Y= \overline{A\oplus M} =AM+A^{'}M^{'}\nonumber\\ =AM+A^{'}(1-M)=\left(A-A^{'}\right)M+A^{'}\nonumber\\ =\left(A-A^{'}\right)\cdot M+A^{'}\cdot 1. $

In Eq. (3), the constant $A^{'}$ is preserved through an AND operation between $A^{'}$ and 1, where the parameter 1 represents the LRS value of memristors. Eq. (3) demonstrates that the constant current associated with $A^{'}$ can be generated by feeding the inverted input $A^{'}$ into a second memristor crossbar array composed of LRS elements. However, utilizing a second memristor array alters the original structure of the single crossbar architecture by expanding it from one crossbar array to two, thereby increasing the overall size of the architecture and introducing additional side effects related to memristor arrays. To retain the benefits of the original single crossbar architecture, we propose an alternative approach that employs a separate circuit using resistors instead of a second memristor array to implement the AND operation ${(A}^{'}\cdot 1)$ in Eq. (3). The proposed schematic circuit for the AND operation between $A^{'}$ and 1 is illustrated in the Fig. 4.

In Fig. 4, the proposed circuit for implementing AND operation $(A^{'}\cdot 1)$ is designed to enhance the performance of the single memristor crossbar architecture in recognizing 10 images of size $32\times 32$. The input vector $A$ has dimensions of $1\times1024$ and the memristor array is structured as $1024\times10$. The input voltage vector is defined as $A= \left[ \begin{array}{cccc} a_0 & a_1 & \dots & a_{1023} \end{array}\!\!\right]$ and is applied into inverters to generate its complement, $A'= \left[ \begin{array}{cccc}{a'}_0 & {a'}_1 & \dots & {a'}_{1023} \end{array}\!\!\right]$. In this circuit, a resistor $R_b$ is used to represent a bit-1 state in the AND operation ${(A}^{'}\cdot 1)$, where $R_b$ is assigned to the value coressponding to the LRS. A total of 1024 resistors $R_b$ are utilized, matching the size of the voltage vector $A^{'}$. The vector $A^{'}$ is then passed through these resistor to implement the AND operation $(A^{'}\cdot 1)$, thereby generating an additional current $i^{'}$component for a single output column. This additional current $i^{'}$ is subsequently duplicated using current mirrors to produce the corresponding additional currents for output columns, forming the vector $I^{'}=\left[ \begin{array}{cccc} {i'}_0 & {i'}_1 & \dots & {i'}_9 \end{array}]\!\!\right]$. The additional currents ${i}^{'}_0$ to ${i}^{'}_9$ are uniform in magnitude and are distributed across the columns of the single memristor crossbar architecture (from column 0 to column 9), to obtain the final output column currents as defined in Eq. (3). The proposed circuit ensures that the single memristor crossbar architecture maintains the AND operation ${(A}^{'}\cdot 1)$ in Eq. (3), effectively mitigating the negative impact of data density.

The circuit for the single memristor crossbar architecture, designed to performs the full Exclusive-NOR function in Eq. (3), is proposed in Fig. 5. This architecture is intended for the recognition of ten $32\times 32$ images with different data densities.

Fig. 5 illustrates the memristor array $M$, which has dimensions of $1024\times10$ to store 10 images. Each image is flattened into a $1024\times 1$ vector and stored in a corresponding column of the memristor array $M$. The unipolar-to-bipolar converter can be implemented using a non-inverting voltage comparator, as illustrated in Fig. 5, where the unipolar input is applied to the positive terminal of the operational amplifier (Op-amp) and compared against a reference voltage $V_r$, which is set to 0.5 V. The Op-amp is powered by $V+ = +1$ V and $V- = -1$ V. When the input is 1 V, the output is $+1$ V; otherwise, when the input is 0 V, the output is $-1$ V.

The input vector $A$ is first processed by a unipolar-to-bipolar converter and subsequently applied to the memristor array $M$ to perform the first AND operation, $\left(A-A^{'}\right)\cdot M$, as defined in Eq. (3). Simultaneously, the input vector $A$ is also applied to the additional circuit for implementing the second AND operation ${(A}^{'}\cdot 1)$, generating a constant current $i^{'}$. The resistor $R_b$ is set to the LRS. The magnitude of the current $i^{'}$ determined by the data contained within the input vector $A$. The current mirrors, consisting of transistors $M_{31}$ to $M_{61}$, replicate the reference current $i^{'}$ to generate additional currents $i^{'}_0$ to $i^{'}_9$, which maintain values consistent with the input vector $A$. The replicated currents are then supplied to the 10 columns of the array $M$. As a result, the total output column currents $i_0$ to $i_9$, generated by the crossbar architecture, incorporate the current contribution form ${(A}^{'}\cdot 1)$, as expressed in Eq. (3). Finally, the total output column currents are fed into a Winner-take-all circuit to identify the maximum output column current, indicating the column that best matches the input pattern $A$. It should be noted that the constant term circuit assumes ideal current mirroring. While mismatch in practical current mirrors is inevitable, the added constant current is distributed equally across all columns. Therefore, mismatch-induced variations affect all columns in a similar manner and the relative differences among column currents, which are critical for the operation of the Winner-Take-All circuit, are largely preserved. This assumption allows us to focus on the architectural-level benefits of the proposed design.

The proposed additional circuit for implementing the AND operation $(A^{'}\cdot 1)$ in Eq. (3) enables the circuit depicted in Fig. 5 to represent all parameters of the full XNOR function. Consequently, as the data density of input vector $A$ decreases, the output column currents of the single crossbar architecture remain stable due to the contribution of the parameter $A^{'}$, which has high data density and supplies a large additional current $i^{'}$ in the full XNOR function. This characteristic ensures that the discharging voltages ${VC}_0$ to ${VC}_9$ of capacitors $C_0$ to $C_9$ are unaffected by the variations in data density, thereby preventing the performance degradation of the Winner-take-all circuit caused by the fluctuations in the data density of the input $A$.

Fig. 4. The proposed circuit for implementing the AND operation of $(A^{'}\cdot1)$ in Eq. (3).

Fig. 5. The proposed circuit for the single memristor crossbar architecture performing the full Exclusive-NOR function to recognize ten $32\times32$ images with different data densities.

III. RESULTS AND DISCUSSIONS

To evaluate the proposed circuit in Fig. 5, we utilize 10 grayscale images to produce black-and-white images with varying data densities. These grayscale images, each sized $32\times 32$, are shown in the Fig. 6.

The grayscale images are converted to black-and-white images with data densities of 0.25, 0.5, and 0.75, as shown in Fig. 7. Images #0, #1, and #2 have low data density of 0.25; images #3, #4, and #5 have moderate data density of 0.5; and images #6, #7, #8, and #9 have high data density of 0.75. A low data density of 0.25 indicates that the number of bit-1 values in the image accounts for 25% of the image, while a high data density of 0.75 indicates that the number of bit-1 values account for 75% of the image.

Fig. 6. The ten grayscale images of size 32×32 used for testing, from image #0 to image #9.

Fig. 7. The black-and-white images: (a) with low data density of 0.25, (b) with moderate data density of 0.5, and (c) with high data density of 0.75.

The 2D image is flattened into a $1024\times 1$ vector and stored in a column of memristor array $M$. The memristor array $M$ has dimension of $1024\times 10$ designed to store 10 binary images. A bit value of 1 is encoded by a memristor in low resistance state (LRS) and a bit value of 0 is encoded by a memristor in high resistance state (HRS). In this work, the proposed memristor circuit in Fig. 5 was simulated using Cadence Spectre circuit simulation ^[31]. The memristor was modeled using Verilog-A implementation, which has demonstrated to accurately replicate the characteristics of real-world devices ^[32], with LRS and HRS set to 100 K$\Omega$ and 10 M$\Omega$, respectively. The crossbar array was programmed using V${}_{\rm DD}$/3 scheme to minimize the unwanted memristance change in unselected cells during write time ^[33]. The input binary image is first converted into a $1024\times 1$ input vector $A$, which is then fed into a unipolar-to-bipolar converter to produce bipolar input voltages of $+1$ V and $-1$ V. These bipolar input voltages are then applied into the memristor array $M$ to perform the first AND operation $\left(A-A^{'}\right)\cdot M$. Simultaneously, the input vector $A$ is applied to an additional circuit to implement the second AND operation $(A^{'}\cdot 1)$ as described in Eq. (3), producing the final output column currents. The output column currents $i_0$ to $i_9$ for recognizing black-and-white images with different data densities are shown in Fig. 8.

Fig. 8. The ten output column currents $i_0$ to $i_9$ of the proposed single memristor crossbar architecture with the column-wise constant term circuit when recognizing 10 black-and-white images with varying data densities.

Fig. 8 illustrates that the output column currents corresponding to low data density (0.25) for image #0, #1, and #2 and moderate data density (0.5) for image #3, #4, and #5 are similar to those corresponding to high data density of 0.75 (image #6, #7, #8, and #9). Notably, the maximum output column currents remain stable at approximately 10 mA across varying densities. This stabilization is resulted from the implementation of full XNOR operation, as expressed in Eq. (3), wherein the parameter ${(A}^{'}\cdot 1)$ is reserved, as analyzed previously. These findings provide strong evidence that the proposed circuit successfully stabilizes the output column currents of the single memristor crossbar architecture, rendering them independent of image data density.

The output column currents $i_0$ to $i_9$ induce the discharge of pre-charged capacitors $C_0$ to $C_9$ in Fig. 5 at different rates, resulting in corresponding decrease in the discharging voltages $VC_0$ to $VC_9$ at different speeds. In this work, the output column currents were evaluated using 50 pF capacitors to measure the discharging voltages. Fig. 9 presents the discharging voltages of the 50 pF capacitors $C_0$ to $C_9$ driven by the output column currents generated by the proposed single memristor crossbar architecture with the column-wise constant term when recognizing image #2 (low data density of 0.25) and image #6 (high data density of 0.75).

Fig. 9. Discharging voltages of the 50 pF capacitors C$_0$ to C$_9$ driven by the output column currents generated by the single memristor crossbar architecture when recognizing: (a) image #2 with low data density (0.25), (b) image #6 with high data density (0.75) using the proposed column-wise constant term circuit.

Fig. 9(a) demonstrates that, despite the low data density of the input image (0.25), the discharging voltages $VC_0$ to $VC_9$ maintain timing characteristic similar to those observed in Fig. 9(b), which represents a high data density input image (0.75). Among these voltages, $VC_2$ exhibits the fastest decrease, while the others discharge more gradually. Notably, a period time of 4 ns, $VC_2$ reaches the threshold of 0.5 V, while the others stay above 0.7 V. Consequently, a pulse is generated, propagating $D_2$ to ${Output}_2$, indicating that the input image matches the stored image #2 in column #2. Similarity, in Fig. 9(b), $VC_6$ dischages the fastest, leading to the activation of ${Output}_6$ for the recognition of image #6. These results indicate that the discharging voltages are no longer negatively affected by reductions in data density. This stable discharging behavior is attributed to the consistent output column currents observed in Fig. 8, which are generated by the proposed single memristor crossbar architecture. Consequently, the Winner-take-all circuit functions correctly under conditions of reduced data density, maintaining the stability of the single memristor crossbar architecture's performance. The output pulses generated by the WTA circuit, along with the corresponding capacitor discharging voltages for low data density (0.25) and high data density (0.75) inputs are also illustrated in Fig. 9

Fig. 10. The discharging voltages of the 50 pF capacitors C$_0$ to C$_9$, driven by the output column currents generated by the single memristor crossbar architecture without column-wise constant term circuit when recognizing image #2 with low data density (0.25).

To analyze the negative impact of data density on the performance of the single memristor crossbar without the column-wise constant term circuit, we examine the capacitor discharge behavior when recognizing image #2 with the data density of 0.25, using the memristor crossbar circuit depicted in Fig. 1(c). In Fig. 3, the maximum current $i_2$ drops to around 3 mA, while other current are nearly zero. Although capacitor $C_2$ discharges the fastest, it fails to reach the threshold within a clock cycle, as shown in Fig. 10. Consequently, no lock pulse is generated and all outputs remain low. In this scenario, the WTA circuit operates incorrectly, as it fails to identify image #2 as the best match for the input image. Therefore, the degradation in output column currents caused by the reduced data density negatively impacts the performance of the single memristor crossbar circuit without the column-wise constant term circuit.

We compare the performances of the proposed single memristor crossbar architecture with a column-wise constant term circuit to the original single memristor crossbar architecture under varying data densities, within the same period of time. The recognition rates of both architectures are presented in Fig. 11.

Fig. 11. Comparison of recognition rates between the proposed single memristor crossbar architecture with the column-wise constant term circuit and the original architecture under varying data densities.

As shown in Fig. 11, the proposed single memristor crossbar circuit with a column-wise constant term achieves a stabilized high recognition rate, while the recognition rate of the original single crossbar architecture decreases significantly as data density decreases. When the data density remains above 0.5, both architectures maintain stable recognition rates, indicating robust performance under high data density. However, when the data density decreases to 0.4, the proposed single memristor crossbar circuit with the column-wise constant term circuit maintains a perfect recognition rate of 100%, whereas the original single memristor crossbar architecture experiences a significant drop to 20%. Notably, at data density of 0.3, the original single memristor crossbar architecture fails to generate an output pulse within the same period of time, resulting in a recognition rate of 0%. The stabilized high recognition rate of the proposed architecture is attributed to the stabilized output column currents, which are enhanced by the constant term circuit under low-density condition, as shown in Fig. 8.

Fig. 12. (a) Statistical distribution of LRS. (b) The recognition rate of four memristor architectures with memristor variation.

Memristance variation is a significant and inherent challenge in memristor crossbar-based neuromorphic circuits ^[34-36]. Variation in both low resistance state (LRS) and high resistance state (HRS) can substantially degrade the accuracy of crossbar circuit. In this work, we conduct a Monte Carlo simulation to compare the image recognition rate of four distinct memristor crossbar architectures under device variation ranging from 0% to 40%. As illustrated in Fig. 12(a), variation modeled using a Gaussian distribution, where a 40% variation implies that the memristance value varied from ($\mu-\sigma$) to ($\mu+\sigma$) k$\Omega$ with a probability of 68% ^[36]. Here $\mu$ is 100 k$\Omega$ and 10 M$\Omega$ for LRS and HRS distribution, respectively. Fig. 12(b) presents a recognition rate of four evaluated memristor crossbar architectures: complementary, twin, single crossbar, and single crossbar with a column-wise constant term circuit. At a high variation of 40%, the complementary crossbar architecture's recognition accuracy degrades significantly to 50.7%. The twin crossbar architecture, which employs two identical crossbar arrays and subtraction mechanism, partially mitigates the effects of memristance variation, achieving a recognition rate of 58.8%. The single crossbar architectures, which employ only one memristor crossbar array, demonstrate greater robustness to memristance variation. As the memristance variation is 40%, both single crossbar architectures remain a recognition rate of approximately 62.1%. These findings highlight that reducing the number of memristors in crossbar circuit, as is done in single crossbar designs, effectively mitigates the impact of device variation, thereby enhancing the reliability of memristor-based neuromorphic systems.

Table 1 provides a comparative analysis of the proposed single memristor crossbar architecture with column-wise constant term against three existing designs: the baseline single crossbar, the complementary crossbar, and the twin crossbar architecture. Conventionally, realizing a synapse requires two memristors, which can be positioned either on the same row or column of a crossbar array, or distributed across two separate arrays. This increases the overall crossbar size, thereby elevating of power dissipation in neuromorphic systems. The proposed single memristor crossbar utilizes only one memristor per synapse, reducing the number of memristors by half. This reduction improves area efficiency and enhances tolerance to device defects and variation ^[29]. As detailed in Table 1, under a 10% device defect rate, single crossbar architectures achieve improve recognition accuracy by 7% and 4% over the complementary and twin crossbar architectures, respectively. Furthermore, under 40% memristance variation, they demonstrate an accuracy improvement of 11.4% and 3.3% compared to the complementary and twin crossbar architectures. The baseline single crossbar architecture, which relies on a simplified XNOR operation, demonstrates substantial improvements in area and fault tolerance. However, its recognition performance significantly degrades with sparse data, as previous reported ^[30]. The proposed single crossbar architecture with the column-wise constant term, in this work, addresses the limitation of the previous work. It preserves the benefits of the simplified single crossbar design while substantially improving robustness to sparse data representation. As shown in Table I, when the data density decreases to 0.4, the baseline single crossbar architecture's recognition rate drop to 20%, whereas the proposed single crossbar architecture with the column-wise constant term maintains a perfect 100% recognition rate under the same condition. This enhancement is achieved by integrating a single crossbar array with the column-wise constant term circuit, enabling the fully implementation of the XNOR operation. As such, the proposed architecture is particularly well-suited for realizing XNOR-based neural networks, which offer advantages in recognition accuracy and memory efficiency.

IV. CONCLUSIONS

In this work, we propose a single memristor crossbar circuit with a column-wise constant term to mitigate the negative impacts of data density in neuromorphic image recognition. An additional circuit is integrated into the single crossbar array to fully implement the XNOR operation. The proposed circuit was evaluated using 10 black-and-white images with data densities of 0.25, 0.5, and 0.75. Simulation results indicate that when the data density is as low as 0.25, the output column currents of the single memristor crossbar architecture with the proposed column-wise constant term circuit are stabilized at levels comparable to those observed with moderate and high data density of 0.5 and 0.75, enabling the Winner-take-all circuit to function correctly. Furthermore, when the data density drops below 0.3, the proposed single memristor crossbar with the column-wise constant term circuit maintains a 100% recognition rate, whereas the single architecture without the column-wise constant term experiences significant degradation, with the recognition rate dropping to as low as 0%. The proposed single memristor crossbar architecture with the column-wise constant term circuit addresses the limitations of the baseline single crossbar design presented in the previous study, while retaining its key advantages. Specifically, it reduces the number of memristors by half and significantly enhances tolerance to device defects and memristor variation. These improvements make the proposed memristor crossbar architecture well-suited for implementing binary and XNOR-based neural networks in embedded system and edge computing platforms.