1. Existing Wafer Warpage Measurement Techniques Based on Optical Systems

Wafer warpage measurement methods can first be classified into contact and non-contact types. Contact methods include the stylus-based method and caliper-based measurement ^[8]. Non-contact methods can be further categorized into Moiré, laser scanning, interferometry, and confocal-based techniques. Moiré methods, including shadow and projection moiré, have been widely used for wafer warpage measurement ^[9,10]. Laser scanning-based methods are also commonly used in practice for warpage measurement due to their broad availability ^[11,12]. Although interferometry-based systems are more expensive, they are capable of measuring in the range of several to tens of nanometers and have been employed for high-precision measurements ^[13]. Confocal scanning systems, while slower and requiring more complex optical setups, also offer high measurement precision and are frequently used in practice ^[14]. A comprehensive review of these various wafer warpage measurement techniques has been provided by Sun and Zhang ^[15]. In the semiconductor manufacturing industry, where high-throughput warpage measurements must be performed on mass-produced wafers using automated equipment, the cost and speed of measurement systems are critical factors in technology adoption. In the case of Advanced Package products, the increasing complexity of packaging structures has led to a wider range of wafer warpages. Accordingly, compared to interferometry-based methods, Moiré and laser scanning-based measurement systems are often more cost-effective for manufacturers.

2. Measurement Methods Based on Wafer Support Configurations

In automated in-line measurement systems for mass production, wafer support configuration is a key design factor. While the optical module focuses on acquiring 3D data, the wafer support configuration directly influences the physical warpage of the sample during measurement. For example, warpage values measured using three supporting pins can differ from those measured using four pins. Therefore, for in-line automated systems, wafer support configuration must be carefully designed and implemented. Based on the wafer support configuration, existing warpage measurement systems can be classified into the following types.

The most technically advanced and cost-intensive method involves gripping and supporting a vertically held silicon wafer in an upright position for measurement. This approach reduces shape distortion caused by gravity ^[16]. A certain equipment supplier currently provides a warpage measurement system capable of measuring the warpage of a vertically held wafer. To the best of our knowledge, this system is the only commercially available solution that enables wafer geometry measurement while the wafer is held in a vertical orientation. The supplier possesses a patent-based technology stack for precision ^[17,18]. Therefore, replicating or implementing equipment that measures warpage with the wafer held in a vertical orientation remains challenging for other suppliers.

Therefore, many warpage measurements are conducted by placing the wafer on a flat stage, and warpage measurement equipment is often developed and supplied based on this configuration. Yoo et al. ^[19] experimentally investigated various wafer support configurations and concluded that, under their experimental conditions, using a flat stage for warpage measurement reduces the effect of gravitational sag. In practice, some of the warpage measurement systems supplied to the industry are designed to operate with the wafer placed on a flat stage during measurement. However, this method can be susceptible to contamination and particle interference originating from the surface of the stage.

In addition, warpage measurements can be conducted by supporting the wafer with three or four pins, lifting it from the stage surface during measurement. Liu et al. described a method that calculates gravity-induced deflection (GID) based on the positions of three supporting pins ^[20]. Yoo et al. also conducted warpage measurement experiments using a pin support method in combination with a flat stage ^[19]. However, in warpage measurement systems used in high-mix, high-volume manufacturing environments, it is practically impossible to accurately calculate the GID for an extremely diverse range of product conditions, which presents a limitation of this method.

Warpage values measured using different methods can vary in both shape and magnitude, even when measured on the same wafer. In practice, semiconductor manufacturers often use multiple types of equipment to perform warpage measurements, and variation in measurement values due to different support configurations must be carefully controlled. This is typically managed through adjustment of mechanical process parameters across equipment types, a practice commonly referred to as Tool-to-Tool Matching.

3. Limitations of Existing Research on LargeScale Chip Warpage Measurement

While wafer warpage measurement techniques each have their own advantages, they are not easily applicable to measuring the warpage of ultra-thin chips attached to dicing tape on a 400 mm RF after dicing. On the other hand, as defects such as non-wet failures caused by chip warpage have emerged as critical yield-degrading factors in both homogeneous and heterogeneous chip stacking processes, there is a rapidly growing demand to precisely measure individual chip warpage immediately after dicing, i.e., just prior to stacking.

Although some studies have analyzed chip warpage behavior after dicing 300 mm wafers, the semiconductor industry still largely relies on curvature data obtained before dicing or on indirect inference methods. Furthermore, studies such as ^[21] have employed finite element analysis (FEA) to simulate chip warpage or used manual measurement tools to inspect each chip individually. However, these methods are impractical in high-throughput production environments where speed is essential. In particular, process variations such as equipment inaccuracies, process fluctuations, and material property changes during actual dicing can cause unique mechanical responses in each chip. Conventional methods fail to capture these variations, making it difficult to accurately reflect the true warpage behavior. Moreover, applying FEA simulations to the vast number of chips produced in mass manufacturing is not a viable solution.

In particular, the warpage state of chips attached to a 400 mm RF using the tape represents a critical intermediate stage in the back-end process. Nevertheless, research on direct measurement solutions capable of capturing chip warpage in this state quickly and simultaneously across multiple chips is almost nonexistent. This technological gap poses a major barrier to fully understanding warpage mechanisms under actual packaging conditions and to developing process control and optimization strategies based on this understanding.

4. Influence of Tape Material Properties on Warpage Behavior

The adhesive strength of dicing tape has a direct impact on the stability of die pick-up during semiconductor manufacturing processes, while other mechanical and thermal properties such as viscoelasticity and the coefficient of thermal expansion can exert indirect influence through temperature variations and stress distribution ^[22]. During thermal cycling and mechanical handling, the material properties of the tape affect interfacial stress distribution, stress relaxation, and peeling behavior, which may indirectly influence the actual warpage profile or residual stress state of the chip ^[23]. Furthermore, it has been reported that as the die becomes thinner, the adhesion to the tape increases, making the peeling process more difficult and potentially preventing the natural warpage of the chip from being revealed while it remains attached to the tape ^[22].

In this study, we propose a method for measuring the warpage of large numbers of chips. Specifically, we introduce a measurement method that evaluates chip warpage in-situ while they remain attached to the dicing tape on a 400 mm RF. Two major technical challenges must be addressed for this measurement concept to be realized. First, due to the sagging of the RF tape under gravity, global warpage of the tape is introduced, which interferes with accurate measurement. Second, the adhesion of the chip to the tape flattens its warpage, preventing the actual warpage from being observed. To overcome these issues, we present a high-throughput chip warpage measurement solution for high-volume manufacturing, based on the UV-induced tape delamination mechanism introduced in Section III and further developed in Section IV.

1. Mechanics of UV-Induced Chip-Tape Delamination

In Section IV, as shown in Fig. 2, this section explains the mechanism behind the thermomechanical warpage and delamination of semiconductor dies induced by UV treatment. This serves as the background for the core idea of the proposed method: using UV exposure to reveal the warpage of individual chips. The thermomechanical behavior at the chip-tape interface under UV irradiation is driven by the difference in coefficients of thermal expansion between the materials. When exposed to UV, both the chip and tape experience a rise in temperature, resulting in thermal stress at the interface. Thermal stress occurs when a material tends to expand or contract due to a temperature change but is mechanically constrained from doing so. In this context, the mismatch in thermal expansion between the chip and tape leads to interfacial stress development. When a material with a coefficient of linear thermal expansion $\alpha$ undergoes a temperature change $\Delta$T, and its expansion is completely restricted, the induced thermal stress $\sigma$ can be expressed as Eq. (1).

where $\sigma$ is the thermal stress generated within the material, $\varepsilon$ is the total strain, $E$ is Young's modulus of the material, which defines its stiffness or resistance to elastic deformation under load. The coefficient $\alpha$ corresponds to the materials coefficient of linear thermal expansion, expressed in units of 1/K, indicating the rate at which the material expands per unit temperature increase. Finally, $\Delta$T is the change in temperature (in kelvin or degrees Celsius) experienced by the material ^[24]. This UV-induced stress development sets the stage for delamination, governed by the interfacial energy dynamics described below. This UV-induced stress development sets the stage for delamination by releasing the inherent chip warpage previously constrained by the tape. Tape adhesion strength can be selectively reduced through UV stimulation. By applying UV irradiation, the adhesive strength can be weakened, enabling easier delamination of chips from the tape. This occurs because UV exposure increases crosslinking within the adhesive, leading to a reduction in its viscoelasticity and tack properties, thereby decreasing adhesion. Lee et al. investigated the conditions required for easily peelable acrylic dicing tapes, particularly focusing on the reduction of adhesion strength after UV exposure in the pick-up process due to polymer network formation ^[23]. Additionally, Wang conducted a study on the strategic design of photoreactive monomers for the development of UV-induced debondable acrylic pressure-sensitive adhesives (PSA) ^[25]. By leveraging these UV-induced structural transformations to lower peel strength, such mechanisms can be applied to the development of chip warpage measurement methods.

Fig. 2. The non-destructive, large-scale chip warpage measurement method.

2. Minimizing Warpage Interference via Uncured Flux Support Layer

As described in Section IV, the proposed method involves placing ultra-thin chips horizontally on a high-viscosity, uncured flux layer, enabling the preservation of the chip's inherent warpage during measurement. The flux, possessing viscoelastic properties, flexibly deforms under the chip's load while preventing localized stress concentrations, thereby helping to retain the chip's natural warpage profile. Since the flux remains uncured, it does not mechanically constrain the chip and is unsuitable for vertical mounting. However, in a horizontal staging system, it effectively serves as a support layer without interfering with the chip. As a result, the flux does not disturb the chip's warpage, allowing for accurate measurement while preserving the original warpage characteristics. Due to the extremely weak mechanical coupling between the chip and the flux in this structure, mechanical interference is minimized rather than promoting stress transmission, which is advantageous for improving measurement accuracy. The following Eq. (2) describes how the warpage of an ultra-thin chip placed on uncured flux is transmitted as stress. The approximate equation (2) is a first-order approximation model based on the fundamental stress-strain relationship for linear elastic materials, $\sigma=E\cdot\varepsilon$. $\varepsilon$ is the strain, which can be approximated as $\varepsilon\approx\frac{w(x,y)}{t_f}$, where $t_f$ is the thickness of the support layer, and $w(x,y)$ is the out-of-plane displacement, or warpage, of the chip at position $(x,y)$. In this model, the support layer is assumed to behave as a linear elastic material, and a small vertical deformation occurs under the chip's load. This equation provides a physically intuitive model for estimating how the warpage of an ultra-thin chip placed on a flexible support layer is transmitted as vertical stress within the layer.

In Eq. (2), $\sigma(x,y)$ represents the compressive or tensile stress, $E_f$ is the Young's modulus of the flux, $w(x,y)$ denotes the warpage (z-direction displacement) of the chip at position $x$ and $y$, and $t_f$ is the thickness of the flux layer. When $E_f$ is small, the resulting stress $\sigma(x,y)$ is also small, allowing the flux to naturally absorb the chip's warpage with minimal interference. Therefore, the smaller the $E_f$, the more the flux behaves like a liquid, flexibly conforming to the chip's warpage and reducing mechanical interference. In this context, applying a large amount of uncured flux with a very low modulus increases the flux thickness $t_f$, and according to the equation, this further minimizes interference and allows better absorption of the chip's warpage. Several studies have shown that a higher Young's modulus increases structural rigidity and thereby reduces warpage through the same mechanism ^[26,27]. In this study, we apply the opposite approach by using uncured flux with a low Young's modulus as a support layer to preserve the chip's inherent warpage during measurement.

1. Chip-Tape Delamination and Vacuum Chucking (CTD-VC) Chip Warpage Measurement Method

CTD-VC refers to a non-destructive, LSCW measurement method based on chip-tape interface delamination control and 400 mm vacuum chucking. As automated material handling (AMH) for 400 mm RF became feasible, the laser sawing process of wafers adopted the 400 mm RF as a baseline, and it is now widely used in semiconductor manufacturing. However, the tape attached to the 400 mm RF tends to sag due to gravity, and after the sawing process, the diced chip-level products remain attached to the tape on the RF. In this state, applying conventional warpage measurement solutions becomes virtually impossible. While various existing optical systems have been developed with a focus on acquiring high-precision 3D data, the two previously mentioned factors, which are the sagging of the tape and the chip's attachment to the tape, physically conceal the actual warpage information of the sample. As a result, conventional measurement methods cannot capture accurate warpage. To overcome this limitation, this study proposes a practical solution, which is described in Fig. 3.

As shown in Fig. 2, the wafer is diced into individual chips after the sawing process. At this stage, UV treatment is applied based on Eqs. (1) and (2) presented in Section III. Upon UV exposure, each chip undergoes partial delamination from the RF tape, which physically reveals the inherent warpage of the individual chips. In addition, to eliminate measurement errors caused by the global shape distortion due to gravitational sagging of the RF tape, the stage holding the 400 mm RF was modified to enable vacuum chucking of the tape. Through vacuum chucking, the tape is flattened, and sag-induced noise is effectively removed.

As a result, this measurement approach enables accurate acquisition of chip warpage by eliminating physical noise caused by tape bonding and sagging. The chips are scanned using a 3D optical module such as a 3D scanner or interferometer, and the acquired data contains sufficient information to calculate the warpage of each chip. After obtaining the 3D signals, reference points such as the chip corners are detected to perform chip-wise alignment, allowing each chip to be mapped to its own local 3D coordinate system as shown in Fig. 3.

Conventional optical systems have spatial resolutions $R_x$ and $R_y$ in the $x$ and $y$ directions, respectively. Given a chip with height $H$ and width $W$, the total number of height signals acquired per chip is approximately $\frac{H}{R_y}\times\frac{W}{R_x}$. Following this, application-specific processing techniques such as filtering only robust signals, masking bump features on the chip surface, or applying alignment algorithms for rapid chip alignment can be employed. However, these additional software applications are not the main focus of this paper and are therefore not discussed in detail. Fig. 4 shows an example of signal from a single chip through actual experimentation.

Through this approach, the warpage of all $N$ chips on a wafer can be measured simultaneously in a single scanning operation. In general, the time required for 3D scanning varies depending on the optical system used, typically ranging from 40 seconds to 5 minutes. Within this time frame, the warpage of all $N$ chips on the wafer can be measured at once.

In addition, the proposed method offers a significant advantage from a mass production perspective. The Auto Visual Inspection (AVI) process, well known in semiconductor inspection, is a widely used inspection solution in many semiconductor manufacturing environments. In the AVI equipment market, dedicated inspection systems for 400 mm RF have already been commercialized and developed over the past decade in response to industry demand. This presents an opportunity to integrate the AVI system with the chip warpage measurement process for combined operation. By installing two cameras on a single turret, the system can be configured with a dual optical setup that enables simultaneous AVI inspection and warpage measurement. Furthermore, the warpage measurement results can be fed back into the AVI inspection process to dynamically control the camera height during the 2D scanning stage. This allows the system to address the well-known focus-out issue in AVI processes. Therefore, the proposed method offers groundbreaking advantages in both semiconductor mass production and process technology perspectives. As a result, the CTD-VC method offers significant advantages as a chip warpage measurement solution from a mass production perspective, not only by enabling accurate chip warpage measurement but also by providing a practical means to address focus-related issues in AVI processes.

Fig. 3. Local and global coordinate system for 3D data.

Fig. 4. Chip data obtained using the proposed method.

2. Flux-based Support Layer (F-SL) Chip Warpage Measurement Methods: Cured Flux (CF-SL) and Uncured Flux (UF-SL) Methods

F-SL chip warpage measurement methods can be classified into two categories, Cured Flux and Uncured Flux Support Layers. The Uncured Flux (UF-SL) method and Cured Flux (CF-SL) method, as described below, are destructive measurement techniques, unlike the first non-destructive approach. In these Methods, bare silicon wafers are patterned via photolithography to replicate the layout of the target chips. After the laser sawing process is completed, the target chips are stacked in a single layer onto the patterned bare silicon wafer. During this process, an excessive amount of flux is intentionally applied between the chips and the wafer. This flux serves as a damping layer to minimize deformation of the chip warpage induced by gravitational forces acting on the support surface.

Since ultra-thin chips after laser sawing are only a few tens of microns thick, they are highly susceptible to warpage caused by their own weight. When such chips are placed directly onto a bare silicon wafer, point or partial contact with the support surface can induce stress concentration, and gravitational deflection can exaggerate the deformation, distorting the original warpage profile of the chip.

To mitigate this, applying a highly viscous flux between the chips and the wafer allows the material to distribute uniformly across the chip surface, forming a continuous support layer. This support layer absorbs shear stress and bending moments, thus suppressing out-of-plane deformation. Flux materials with viscoelastic properties provide not only cushioning against external mechanical forces but also effective stress redistribution.

Moreover, the flux fills micro-scale mechanical gaps between the chips and the bare wafer, enabling uniform support across the entire chip surface. This configuration helps ensure that the measured warpage characteristics more accurately reflect the inherent deformation of the chips.

However, the UF-SL method is applicable only to measurement systems that utilize horizontal staging configurations. This is because the measurement is performed prior to the thermal curing of the flux, meaning that the flux remains in a non-cured, viscous state during the process. In this uncured state, the flux cannot withstand gravitational forces to maintain the chips' positions reliably. As a result, vertical staging systems are not compatible with this method, since the chips would shift or collapse under gravity. Therefore, this technique is incompatible with measurement systems based on vertical wafer staging.

The CF-SL method is designed to enable chip warpage measurement even in metrology systems that utilize vertical staging. Like the UF-SL method, it involves stacking the chips onto a bare silicon wafer and applying flux between them. However, this approach adds a thermal curing step to solidify the flux layer. During the curing process, the intrinsic warpage of each chip induces subtle mechanical deformation, which is transmitted through the hardened flux layer to the underlying silicon wafer. As a result, localized stress distributions are generated on the backside of the bare wafer. By precisely measuring these localized stress patterns, the warpage characteristics of each chip can be indirectly inferred.

The CF-SL method is based on the principle that stress induced by chip warpage is transmitted through the cured damping layer to the supporting substrate. Accordingly, it constitutes an indirect measurement technique that offers compatibility with vertical staging systems. In particular, by analyzing the stress distribution on the backside of the substrate, it becomes possible to indirectly estimate the subtle mechanical deformation of each chip. Therefore, this CF-SL Method is regarded as having the potential to be implemented in high-precision interferometry-based equipment. However, precise experimentation is required to evaluate the feasibility of accurately estimating warpage, as the effectiveness of this approach heavily depends on the resolution of stress transmission and the sensitivity of the interferometric system.