1. Previous Work

In 1979, G. L. Baldwin and J. L. McCreary first utilized a binary-weighted matched capacitor array along with an operational amplifier to form a capacitive voltage divider network, achieving precise attenuation ^[2]. In 2017, Nai-Chen Chen et al. proposed a novel Metal-Oxide-Metal (MOM) capacitor structure, which offered advantages such as high capacitance density and low parasitic capacitance compared to all other capacitor structures. Based on the MOM capacitor, they further introduced a capacitor sizing and interconnect parasitic matching method based on integer linear programming ^[3]. In 2021, Keun-Yong Chung, Kwang-Hyun Baek, and Bo-Kyong Choi proposed that parasitic capacitance from top to bottom would reduce the linearity of SAR ADCs, and designed two customized routing capacitors to reduce parasitic effects between capacitor arrays ^[4]. In 2024, Zheng-Han Chen and colleagues proposed a novel capacitor layout structure that bottom plate wraps top plate except the upper surface, effectively reducing the parasitic capacitance of the sub-CDAC top plate ^[5]. In the same year, Sewon Lee and colleagues proposed a grounded-finger CDAC that employs a regularized structure with symmetrical top plates on both sides to mitigate the impact of non-scalable edge capacitance ^[6]. Based on the above research, this article designs a symmetrical MOM capacitor with a bottom plate wrapped around a top plate for experimental purposes.

In order to cope with parasitic effects introduced by wiring, layout technology is crucial, and as design complexity increases, automated layout tools become necessary. In 2013, Mark Po-Hung Lin et al. proposed the Pair-Sequence placement method to effectively reduce parasitic effects caused by interconnect lines in capacitor array layouts ^[7]. In 2016, Florin Burcea et al. proposed a new chessboard placement method for capacitor arrays by minimizing the variance of differential nonlinearity (DNL) ^[8]. In 2020, Ye X. Ding et al. proposed a hybrid placement combining chessboard and grouped placements, taking into account the complexity of capacitor routing and the generalized nonlinear model ^[9]. In 2021, Mingjie Liu and colleagues introduced OpenSAR, the first open-source automated end-to-end SAR ADC compiler. This compiler utilizes a template-based layout generator that arranges the LSB and MSB sections of the capacitor array in interleaved rows and columns, respectively ^[10]. In the same year, Jaeduk Han and colleagues implemented on-grid placement and routing using LAYGO, a Python-based layout-generation engine, which showcased the potential of scripting processes ^[11]. In 2022 and 2023, Yao-Hung Tsai and Shen-Iuan Liu introduced digital place-and-route (DPR) tools to complete the layout of SAR ADCs ^[12,13]. In 2023, Nibedita Karmokar et al. first proposed a model to balance linearity metrics and the 3-dB frequency of binary-weighted DACs. They also introduced two different placements: the spiral placement and the BC placement ^[14]. In 2024, Costas Laoudias and his team ensured good linearity in their capacitor array design by separately laying out the MSB and LSB arrays. They positioned the split capacitors between these two arrays, significantly reducing the area occupied by the CDAC ^[15].

References ^[5,7-9,14] all aim to minimize matching errors and parasitic coupling through specific unit arrangement rules. ^[15]'s partition layout focuses on optimizing area and key position matching. These methods demonstrate the decisive impact of intelligent layout on CDAC performance, but they typically exist as independent design rules or manual optimization steps. Based on the above research and the customized capacitor structure proposed in this article, a grouping based staggered arrangement scheme between columns is adopted. ^[10-13] represents a significant progress towards automated and efficient design, demonstrating the feasibility of automated design of capacitor arrays. Based on this, this article designs an automated layout generation strategy based on staggered arrangement between columns, which is highly regular in layout and has a simple and efficient algorithm. The ultimate simplicity and automation friendliness, while ensuring good performance, are the main advantages and differences of this solution compared to more complex strategies ^[10-13] in terms of automation implementation.

2. Our Contributions

This paper implements an automatic generation method for high-matching capacitor array layouts based on EDA technology. It includes a complete automatic layout design process and its algorithms. For CDAC layout designs with 12-bit precision or below, the layout generation time is reduced to the level of seconds. In CDAC designs with 8 to 13 bits, the effective number of DAC bits (ENOB) can approach the ideal value. This method significantly shortens the design cycle and improves work efficiency while achieving high-precision layout generation. With the assistance of EDA technology, designers can quickly complete complex CDAC layout designs, reduce manual operation time, and minimize parasitic effects and delays caused by human errors or intuitive experience.

In the next section, we will introduce the unit capacitor used and analyze the circuit model of the CDAC array after parasitic extraction. In the third section, we will present the implementation of the CDAC placement algorithm. In the fourth section, we will demonstrate the detailed routing method for the capacitor array. In the fifth section, we will showcase the experimental results of the automatic layout generation. Finally, in the sixth section, we will summarize our work and discuss potential improvements for the layout.

1. Capacitor Structure

The process used in this article is TSMCN65, and the MIM capacitor shape of this process is polygonal, which is not conducive to the design of automatic layout and routing tools, and its structure is easily affected by external environment. Therefore, this paper uses custom MOM capacitors as the unit capacitors for designing the CDAC array. MOM capacitors are capacitors realized through multi-layer metal interconnection structures. Typically, they adopt a finger-like structure, where metal wires of the same layer are arranged in parallel, and the capacitive coupling is enhanced by sidewall coupling. A typical design of MOM capacitors involves vertical stacking, with vias connecting different metal layers, utilizing the overlapping area between layers to form capacitance. A schematic diagram of the MOM capacitor structure is shown in Fig. 2.

Fig. 1. The MIM capacitor of TSMCN65.

Fig. 2. The schematic diagram of the MOM capacitor structure {^[16].

MOM capacitors can be directly fabricated using the metal layers and oxide dielectric materials from standard CMOS processes, without the need for additional masks. This makes the manufacturing process simpler and more cost-effective, and easier to produce, ultimately reducing production costs ^[16]. In addition, MOM capacitors offer several advantages, including high matching accuracy, low parasitic parameters, and excellent stability with respect to temperature and voltage. These characteristics make MOM capacitors ideal for precision applications such as CDACs, where accurate capacitance values and reliable performance under varying conditions are crucial.

Process variations, such as lithography misalignment and etching non-uniformities, typically exhibit a gradient characteristic in space (e.g., metal lines on the left side tend to be wider, while those on the right side tend to be narrower). To address these variations, MOM capacitors can be designed using a co-centric symmetric placement. This design ensures that each capacitor unit is distributed across different spatial positions, helping to average out local deviations. As a result, the ratio of adjacent capacitors can closely approach the ideal value. This capability to minimize local process variations and maintain high matching accuracy is a key advantage that makes MOM capacitors irreplaceable in high-precision SAR ADCs.

One of the main sources of noise in SAR ADC circuits is sampling noise. The magnitude of sampling noise is inversely proportional to the capacitance value, meaning that increasing the capacitance value can significantly reduce the noise amplitude and improve the signal-to-noise ratio (SNR). Larger capacitors are less affected by process fluctuations during manufacturing, leading to a smaller impact on the overall capacitance value. This results in improved matching of the capacitor array, reducing nonlinear errors and ensuring higher accuracy in the output analog signal.The parasitic capacitance in a CDAC is typically in parallel with the designed capacitance. If a larger unit capacitor is chosen, the proportion of parasitic capacitance becomes smaller, reducing its impact on the capacitance ratio. Therefore, using larger capacitors in CDACs offers advantages such as improved accuracy, reduced noise, and enhanced immunity to interference, making them particularly suitable for applications with strict requirements for signal-to-noise ratio (SNR) and linearity. Although this may sacrifice some speed and area, with proper design, these limitations can be partially mitigated, allowing for high-performance digital-to-analog conversion.In CDAC design, a unit capacitance of typically 5.05 fF is used to ensure low power consumption ^[17]. After comprehensive consideration, this paper simulates using a MOM capacitor with a capacitance value of 9.978 fF. The linearity of a capacitor array directly depends on the matching accuracy of the unit capacitance, and the relative error (rather than absolute error) of all capacitor units in the array must be extremely small. This paper uses Metal6 (M6) as the top and bottom plate metals for the capacitor, while Metal5 and Metal7 form two large plates that surround the top plate metal and connect to the bottom plate metal through vias. This structure of the bottom plate enclosing the top plate uses the bottom plate as an electrostatic shielding layer, so that the electric field lines of the top plate terminate at the bottom plate. Therefore, the parasitic capacitance of the top plate of the capacitor is only left with the expected parasitic coupling between the bottom plate, and the parasitic capacitance affected by the external environment is greatly suppressed, thereby ensuring that the parasitic capacitance error of all capacitors is sufficiently small. The specific layout structure is shown in Fig. 3, and the detailed structure of the unit capacitor from a 3D perspective is shown in Fig. 4.

Fig. 3. MOM capacitor layout and its physical dimensions.

Fig. 4. Structure of the unit capacitor (3D capacitor).

This article uses a unit capacitance of 10fF mainly due to laboratory simulation experience, hoping to effectively reduce random mismatches by increasing the capacitance area. And from the data in the table, it can also be seen that CDAC based on 10fF unit capacitance has better performance in terms of linearity.

2. Parasitic Analysis of CDAC Array Interconnects

According to ^[18], in a capacitor array, in addition to the designed capacitance values, there are typically some unavoidable parasitic capacitances that may affect the matching, linearity, and overall performance of the array. There are mainly four types: the parasitic capacitance between the capacitor top plate and the substrate C${}_{\rm TS}$, the parasitic capacitance between the capacitor bottom plate and the substrate C${}_{\rm BS}$, the mutual coupling capacitance between adjacent capacitors C${}_{\rm BB}$, and the additional parasitic capacitance between the capacitor top plate and bottom plate C${}_{\rm TB}$. Taking a 4-bit single-ended capacitive SAR ADC as an example, the equivalent circuit of its CDAC array after parasitic extraction is shown in Fig. 5.

Fig. 5. The equivalent 4-bit SAR ADC circuit after post-layout parasitic extraction.

The performance of a CDAC is closely related to the accuracy of the capacitance ratios in the binary-weighted capacitor array. The precision of these capacitance ratios depends on the matching characteristics of the capacitor array placement and the inductive parasitic effects between the interconnect lines ^[18]. The matching characteristics of the capacitor array placement require the CDAC capacitors to use a highly symmetric co-centroid placement. The inductive parasitics between the interconnect lines primarily affect the accuracy of the CDAC, especially the parasitic capacitance between the top plate and the bottom plate, as well as the parasitic capacitance between the top plate and the substrate ^[19]. A rational placement of the array is necessary to ensure that these two parasitics are in accordance with the capacitance ratio.

In this paper, unit capacitors are designed by splitting a single capacitor in the CDAC into multiple unit capacitors. The number of unit capacitors in the array corresponds to the capacitance ratio in the CDAC, ensuring high matching of the parasitic capacitance between each capacitor's top plate and the substrate. To reduce the parasitic capacitance coupling between the bottom plate interconnects and the top plate, the unit capacitors in this design adopt a structure where the bottom plate surrounds the top plate. The bottom plate routing is done under the capacitor's bottom layer, ensuring a more compact and uniform capacitor array. However, this structure increases the parasitic coupling between adjacent bottom plates. Therefore, the parasitic capacitance between the top plate and the bottom plate may also be influenced by the parasitic capacitance between the adjacent bottom plates.

The MOM capacitors used in this paper have a small parasitic contribution between the bottom plates of adjacent capacitors in the vertical direction, and under design rule check (DRC) distances, they have no significant impact. Therefore, the parasitic capacitance between adjacent capacitor bottom plates mainly occurs in the horizontal direction. When the adjacent capacitors belong to different bits, their bottom plates are connected to different inputs, both of which are strong sources. As a result, the parasitic capacitance between the bottom plates of the two capacitors does not affect the design. However, when the adjacent capacitors belong to the same bit, the parasitic effect between their bottom plates cannot be ignored. This is equivalent to adding a small capacitor in series in the original circuit, which reduces the parasitic capacitance between the bit's capacitor and the top plate. Therefore, the placement in this paper mainly focuses on the adjacent capacitors within the same bit in the horizontal direction to control the total parasitic capacitance between each bit's capacitor and the top plate, ensuring it is close to the capacitance ratio.

1. CDAC Bottom Plate Routing Method

Reviewing the content of Section II.2, the parasitic capacitance between the top plate and the bottom plate can significantly affect the accuracy of the CDAC. The traditional wiring method next to the capacitors usually requires longer connections, which introduces larger parasitic capacitance and resistance, affecting signal transmission speed and further impacting the matching of the capacitors. At the same time, wiring next to the capacitors requires metal lines to bypass the capacitors, occupying additional chip area and affecting the compactness of the array. In contrast, using the metal layer beneath the capacitors for routing while using higher-level metal for the capacitors themselves allows for vertical space reuse, greatly saving the area of the capacitor array. The shortened routing length reduces the impact of parasitic parameters, and the presence of the capacitor bottom plate further reduces the parasitic effects between the routing and the top plate, making it easier to achieve capacitor matching. Additionally, routing beneath the capacitors ensures that the physical environment around each unit capacitor is the same, reducing the impact of mismatch and parasitic effects. Therefore, this paper chooses to route the bottom plate beneath the capacitors.

Considering that the unit capacitor count in a binary-weighted capacitor array is large and the overall layout area is substantial, this paper chooses to route all bottom plate wires vertically to the very bottom of the entire array before making the connections, in order to save space for horizontal routing channels and reduce the overall array area. In integrated circuit design, capacitor arrays typically use a layered layout method with horizontal and vertical lines, to avoid crossing and unnecessary routing, reducing routing complexity, optimizing array area utilization, and minimizing the impact of parasitic effects. In summary, this paper uses Metal4 and Metal3 as the routing layers for the vertical and horizontal lines of the capacitor bottom plate, respectively.

This paper uses the metal layer beneath the capacitors for routing, with vias ensuring the connectivity between the metal lines and the capacitors. In the case where there are multiple vertical routing lines beneath the capacitor, placing the metal line at the center of the capacitor ensures that the parasitic effects are more evenly distributed across both ends of the capacitor. Considering that longer lines generally have larger parasitic coupling, this paper places the longer lines at the center of the capacitor, while shorter lines are placed closer to the edges. The bottom routing structure of the DUMMY capacitors is the same as that of the actual working capacitors, ensuring that the impact of the DUMMY capacitors on the surrounding environment is the same as that of the internal capacitors, and ensuring that the environment around the actual working capacitors near the edges is the same as that of the internal capacitors. The bottom plate of the DUMMY capacitors is uniformly grounded, ensuring that all DUMMY capacitors form the same parasitic effects and have a consistent impact on the surrounding environment, while also forming a good shielding layer to prevent external noise interference. The specific routing implementation pseudocode is shown in Algorithm 2. Taking an 8-bit CDAC array as an example, the routing result of the bottom plate is shown in Fig. 7, where "D" represents the DUMMY capacitor.

Fig. 7. Layout diagram of capacitor array bottom plate routing.

Algorithm 2: Detailed routing algorithm for capacitor array.

2. CDAC Top Plate Routing Method

For the top plate routing, this paper uses Metal6 to route horizontally at the top plate of each row of capacitors and connects them at the left and right ends of the array through vertical metal lines. In this case, the physical environment around each unit capacitor is the same, and there is no intersection between the top plate metal lines and the bottom plate metal lines. The top plates of the DUMMY capacitors in the first and last rows are not connected to other capacitor top plates, in order to prevent the additional parasitic effects of the edge capacitors. This paper grounds their top plates uniformly to isolate external interference signals and prevent noise from coupling into the working capacitor array. The schematic of the top plate routing is shown in Fig. 8.

Fig. 8. Layout diagram of capacitor array top plate routing.

3. CDAC Shielding Layer Routing Method

Through experiments, it was found that even with the method of routing the bottom plate with the metal layer beneath the capacitors to reduce the coupling between the top plate and bottom plate routing, the parasitic capacitance between them still has a certain impact. In this paper, a wider metal layer, which is on the same layer as the bottom plate routing, is added as a shielding layer between adjacent capacitors. This transforms the parasitic coupling between the bottom plate routing and the top plate into the coupling between the bottom plate routing and the shielding layer metal, further isolating the impact of the bottom plate routing on the capacitance value and making it easier to achieve capacitor matching. The schematic of the shielding layer routing is shown in Fig. 9. Taking a 12-bit CDAC with various sizes as an example, the ENOB before and after adding the shielding layer is shown in Table 2.

Fig. 9. Layout diagram of shielding layer.

As mentioned in Section II.2, the parasitic effects between interconnects on the accuracy of CDAC mainly include the parasitic capacitance between the top and bottom plates, as well as the parasitic capacitance between the top and substrate. The top plate of the capacitor in this article is wrapped by the bottom plate, so the parasitic effect between the top plate and the bottom plate plays a major role, and the additional parasitic effect introduced by the shielding layer is relatively small. From the data in the table, it can also be seen that when the shielding layer is added to the layout, its linearity performance is better than that without the shielding layer. From the data in the summary table, it can be concluded that adding a shielding layer effectively isolates the parasitic coupling between the capacitor top plate and bottom plate routing, improving the effective bit resolution of the layout. Furthermore, the stronger the parasitic effects between the top plate and bottom plate routing, the better the shielding layer improves the accuracy of the array.