I. INTRODUCTION

Edge artificial-intelligence-of-things (AIoT) devices which typically remain in standby mode requiring high computing capacity, urge the development of ultra-low leakage and high-density on-chip SRAMs to maximize battery life ^[1]. This demand has driven advances in CMOS architecture, such as nanosheet FET, to support larger memory capacity with a reduced supply voltage ($V_{\rm DD}$) at recent 2-nm technology node ^[2]. Despite this effort, the scaling trend of bitcell area, off-leakage ($I_{\rm OFF}$), and $V_{\rm DD}$ have saturated, as shown in Fig. 1. Additionally, structural channel segmentation and reduced heat transfer path in 3D stacked devices cause severe self-heating effects ^[3] and constraints to implement large capacity of on-chip memory with high energy efficiency.

Fig. 1. Scaling limitations of high-density bitcell area, $I_{\rm OFF}$ and $V_{\rm DD}$ in conventional CMOS technology.}

To address this issue, recent studies for low-leakage SRAMs are reported in legacy node ^[4], using extra supply voltage level or adopting body-biasing scheme ^[5]. However, these approaches do not fundamentally solve the trade-off between power and area efficiency required for energy-constrained edge processors.

One promising alternative is the multi-valued logic (MVL), where the logic system extends beyond binary to higher radix values, enabling improved data density and reduced power consumption by decreasing the number of interconnections ^[6]. In our previous works, leakage and bit-density scalable Ternary-CMOS (T-CMOS) technology using a retrograde profile was reported with 110-nm 4T latch ^[7], 6T trit-cell ^[8], 28-nm CMOS foundry ^[9], and demonstrated up to CIM macro ^[10].

In this work, we propose a highly scalable T-CMOS using a localized halo profile. By tuning halo dose/energy/tilt angle, the short-channel effect immune device characteristics and leakage scalability data are presented. Through the enhanced design window of halo T-CMOS, high-density 6T Ternary-SRAM (T-SRAM) is demonstrated with sub-pA leakages at $V_{\rm DD}= 0.5$ V.

II. T-CMOS BY EXPLOITING HALO PROFILE

We successfully fabricate T-CMOS using an optional mask that employs a halo profiles in 28-nm process, as shown in Fig. 2(a). The fabrication process was carried out by following a sequence of steps: shallow trench isolation (STI) formation, well/channel implantation, gate stack and spacer formation, halo/extension implantation, source/drain (S/D) implantation, spike annealing, silicidation, and back-end-of-line (BEOL). It should be noted that the 28-nm CMOS process used in this work is based on a gate-first high-k metal gate (HKMG) process with a MIPS (Metal-Inserted Poly-Silicon) gate structure. For TCAD process simulation, the gate stack was simplified as SiO${}_{2}$/poly-Si structure. By tuning dose/energy/tilt angle of the halo doping mask, a highly-doped p-n tunnel junction is formed below the channel region which generates band-to-band tunneling (BTBT)-based off-leakage current ($I_{BTBT}$). The picoampere-level $I_{BTBT}$ is successfully obtained at both 28-nm ternary-nMOS (Tn) and ternary-pMOS (Tp) with $10\times$ lower leakage than conventional binary one (Fig. 2(b)). The exponential dependence of tunneling leakage and $V_{\rm DS}$ implies dramatic scaling of static power consumption through $V_{\rm DD}$ scaling. Therefore, our T-CMOS technology significantly reduces dynamic power consumption at a scaled $V_{\rm DD}$ ($< V_{\rm T}$) of 0.5 V, while simultaneously boosting the bit density in on-chip memory using the same 6T latch cell configuration design as the CMOS one, which is shown in Fig. 2(c).

Fig. 2. The 28-nm T-CMOS (vs. CMOS): (a) Highly-doped halo profile is formed below the channel region with specific dose (D) / energy (E) / tilt angle (A) condition. (b) $I_{\rm DS}$-$V_{\rm GS}$ curves at $V_{\rm DS}= 0.05$ V, 0.5 V. (c) $V_{\rm IN}$-$V_{\rm OUT}$ at scaled $V_{\rm DD} < V_{\rm T}$ with ternary inverter schematic and symbol. TVT: Ternary-$V_{\rm T}$ mask.

III. SCALABILITY OF HALO T-CMOS

1. Leakage Scaling by Tuning The Halo Profile

Halo T-CMOS exhibits a higher $V_{\rm T}$ than retrograde one at the same I/I dose due to the formation of a more localized doping profile below the channel region. This $V_{\rm T}$ increases further in short-channel devices, where localized halo implants near S/D extensions merge. As a result, $V_{\rm T}$ roll-off typically observed in CMOS is gradually mitigated by applying retrograde T-CMOS and nearly eliminated in halo T-CMOS indicating improved short-channel behavior (Fig. 3(a)).

Fig. 3. (a) Short channel behavior of halo/retro T-CMOS and CMOS. (b) Comparison of $V_{\rm T}$ and $I_{\rm BTBT}$ with various ion dose conditions. Enhanced channel control of halo profile enables $I_{\rm BTBT}$ reduction with a reduced dose compared to retrograde one. LD/HD: low/high ion dose.

More importantly, the higher $V_{\rm T}$ of halo T-CMOS at the same dose condition enables further leakage suppression by allowing the use of reduced dose levels while maintaining an equivalent $V_{\rm T}$ to retrograde case (Fig. 3(b)). Additionally, retrograde T-CMOS exhibits asymmetric BTBT current levels between Tn and Tp at the same $V_{\rm T}$, primarily due to junction depth difference that modulate the effective doping concentration at the tunneling junction. Thus, it is expected that halo-based doping profiles are more advantageous for short-channel T-CMOS design, offering both symmetric and scalable control of BTBT leakage current.

We newly found that increasing halo energy leads to a notable $V_{\rm T}$ enhancement, which is in contrast to the conventional retrograde case, where higher energy typically reduces $V_{\rm T}$ due to the formation of a deeper tunnel junction from channel region. This increased $V_{\rm T}$, enabled by high halo energy condition, provides additional design room for leakage scaling. In the Tn, high energy of boron induces a channeling effect through the poly-Si gate, thereby raising the doping concentration near the channel surface (Fig. 4(a)). Based on well-calibrated TCAD process simulation, we analyzed that the channeling effect selectively elevates the channel doping concentration while preserving a similar impurity level near the S/D extensions. Therefore, $V_{\rm T}$ is increased with consistent level of $I_{BTBT}$, which is favorable for achieving further leakage suppression under low dose (LD) conditions as shown in Fig. 4(b).

Fig. 4. The scalability of $I_{\rm BTBT}$ according to halo energy. Tn: (a) The channeling effect of HE halo implant primarily increases doping concentration near channel region, resulting in similar $I_{\rm BTBT}$ levels with LE one in (b). Tp: (c) Arsenic ions at HE level diffuse lateral direction below the channel region, leading to $I_{\rm BTBT}$ reduction in (d). LE/HE: low/high ion energy.

In addition, we found that leakage scaling by high halo energy is more effective in the Tp. Due to the heavier atomic mass of arsenic, which channeling effect can be negligible, larger tilt angles are initially applied in conventional p-type FET to localize dopants near the S/D extensions. When halo energy is increased, arsenic ions penetrate beyond the S/D extensions and form highly-localized doping profile below the channel region. This profile increases $V_{\rm T}$, while tunneling leakage is even decreased due to the formation of gradual doping profile near S/D extensions, as shown in Figs. 4(c) and (d).

Increasing the halo tilt angle serves an additional design knob for further BTBT current scaling by enabling additional elevation of $V_{\rm T}$. In high tilt angle, more localized channel doping profiles are formed for both Tn (Fig. 5(a)) and Tp (Fig. 5(c)). However, higher $I_{BTBT}$ is observed in Tp at high tilt angle condition due to the increased doping concentration near channel-adjacent S/D extensions. Despite this intensified junction profile, accompanying elevation of $V_{\rm T}$ effectively compensates for increased $I_{BTBT}$, offering additional design space to demonstrate low-leakage T-CMOS. (Fig. 5(b) and (d)).

Fig. 5. The scalability of $I_{\rm BTBT}$ with halo tilt angle. Tn: (a) Increased tilt angle forms a highly-localized doping profile at the center of sub-channel region, leading to substantial leakage scaling in (b). Tp: (c) Highly tilted ion increases the doping level of both the channel and S/D edge regions, leading to further dose scaling in (d). LA/HA: low/high ion tilted angle.

2. Enhanced Design Window of Halo T-CMOS

Figs. 6(a) and 6(b) present the design window of ternary devices according to $V_{\rm T}$ and $I_{BTBT}$ data for both Tp and Tn. By leveraging multiple design parameters of halo profile including dose, energy, and tilt angle, 28-nm halo T-CMOS features leakage-scalable and robust ternary functionality across a wide sub-$V_{\rm T}$ regime. Owing to this enlarged design window, ternary operation is experimentally demonstrated at various $V_{\rm DD}$, including low-leakage 0.5 V operation with sufficient noise margin of 2k${}_{B}$T and even ultra-scaled 0.3 V operation (Fig. 6(b)). This confirms that halo-based T-CMOS technology is applicable to a broad area from ultra-low power, battery less sleep-mode systems to mainstream logic and memory applications with nominal $V_{\rm DD}$.

Fig. 6. (a) Comparison of $V_{\rm T}$-$I_{\rm BTBT}$ design window for 28-nm halo and retrograde T-CMOS. Dashed line shows target specification of T-CMOS to implement optimal ternary operation. (b) Measured ternary inverters from 1.0 to 0.3 V.

In addition, we experimentally demonstrated variation tolerance of 28-nm T-CMOS inverter with retrograde doping profile by verifying the feasibility to match Tn and Tp on large-scale 300-mm silicon wafers ^[9]. Compared to retrograde profile, halo doping can reduce channel doping level while maintaining the same $I_{\rm BTBT}$/$V_{\rm T}$ design owing to its locally confined profile near S/D junction. Therefore, it can be expected that the halo T-CMOS provide more stable and robust ternary operation than prior retrograde one.

IV. LOW-LEAKAGE AND HIGH-DENSITY TERNARY-SRAM

By using SPICE compact model of T-CMOS ^[8], we demonstrate a 28-nm ternary on-chip memory cell. As shown in Fig. 7(a), our T-CMOS inverter features ultra-low power ternary operation at a scaled $V_{\rm DD}$ of 0.5 V, achieving a 63% reduction in leakage current compared to CMOS averaged across both binary and ternary data storage states. Owing to the exponential dependence of $I_{\rm BTBT}$ and $V_{\rm DS}$, 93% lower standby leakage is achieved in ternary data storage. To maximize area efficiency, we leverage a foundry-provided high-density 6T bitcell, enabling 50% higher memory cell density by storing 1-trit (1.5 bits) in the same 6T configuration shown in Fig. 7(b). Table 1 shows benchmarking results against other low leakage bitcell ^[11-13]. Our 28-nm 6T T-SRAM exhibits the lowest leakage power of 0.62 pW/bit, achieving a 22.5% reduction compared to the 0.4 V bitcell (0.8 pW/bit) in ^[11], and demonstrates the best figure of merit (FoM), defined as cell density divided by the leakage power.

Fig. 7. (a) Scalable leakage and (b) cell density characteristics of 6T T-SRAM with same layout design of foundry 6T bitcell.

In terms of read/write margins of proposed T-SRAM, the static noise margin (SNM) of binary and ternary inverters should be evaluated, since it serves as a fundamental metric for both read and write stability. In ideal cases, a ternary inverter requires $1.5\times$ higher $V_{\rm DD}$ than a binary inverter to achieve the same SNM. Owing to the subthreshold operation principle, the proposed 0.5 V T-SRAM can provide similar noise margins to that of a 0.4 V 28-nm bitcell ^[11] by exploiting low thermal budget process and S/D extension underlap engineering.

Moreover, our T-CMOS technology is more preferably applicable to advanced device structures such as FinFET and GAAFET since the channel and BTBT junction can be completely separated ^[14]. Specifically, by employing ground-plane (GP) ^[15] and punch-through stopper (PTS) doping techniques ^[16], constant tunneling leakage in the sub-fin or bottom transistor regions can be obtained in advanced 3D Fin or GAA structure for stable T-CMOS operation.

VI. CONCLUSION

We have experimentally demonstrated highly scalable 28-nm halo T-CMOS technology. By tuning ion dose, energy, and tilt angle, we verified scalable tunneling leakage and subthreshold ternary operation with an expanded design window. The low-leakage 6T T-SRAM was implemented, boosting information density to 1.5-bits per cell. Therefore, the proposed halo T-CMOS technology offers a promising solution for always-on edge applications and wireless sensor nodes by enabling longer system lifetimes and reduced silicon footprint.