I. INTRODUCTION

As the semiconductor industry has advanced, semiconductor products have become increasingly miniaturized. As a result, they exhibit superior characteristics in terms of performance and area. However, with the development of high-integration technologies, the risk of semiconductor device damage due to Electro-Static Discharge (ESD) has also increased. Consequently, ongoing research on ESD protection circuits to prevent damage to IC circuits caused by ESD is being conducted ^[1]. 4H-Silicon Carbide (SiC) is a material with a wide bandgap that allows operation at high temperatures up to 600$^\circ$C, exhibiting fast switching speeds, low on-resistance, and excellent high-temperature characteristics ^[2,3]. However, SiC has an electrical field strength approximately 10 times higher than that of Si, and its forward voltage drop is about three times greater than Si ^[4,5]. Considering these characteristics, research is needed to optimize and improve the reliability of SiC-based ESD protection circuits ^[6,7]. Among existing Si-based ESD protection circuits, GGNMOS is widely used due to its excellent compatibility with CMOS processes and its simple structure. When an ESD surge is applied to the Drain terminal of a GGNMOS, an Avalanche Breakdown occurs, which causes the internal parasitic NPN BJT to discharge current, resulting in a Snapback characteristic ^[8]. When designing an ESD protection circuit based on 4H-SiC, the higher bandgap and higher breakdown voltage lead to an increase in the voltage at which Avalanche Breakdown occurs, thereby raising the trigger voltage and strengthening the Snapback characteristic ^[9-11]. The trigger voltage is one of the most important characteristics in ESD protection circuit design ^[12,13]. ESD protection circuits must operate within a voltage range lower than the breakdown voltage of the IC circuit, considering the ESD Design Window. Therefore, more optimized trigger voltage control technology is needed to design 4H-SiC-based ESD protection circuits.

II. PROPOSED ESD PROTECTION CIRCUIT

Fig. 1(a) shows the cross-sectional view of the conventional GGNMOS structure. The operation principle of the conventional GGNMOS is as follows. In the normal state, when no ESD event occurs, the conventional GGNMOS remains inactive due to the reverse bias. However, when an ESD event occurs and an ESD surge enters the Anode terminal, the potential of the N+ region rises. As the ESD surge continues to enter the Anode terminal, the potential of the N+ region increases progressively, and when it reaches the threshold, Avalanche breakdown occurs at the junction between the N+ and P-Well. The electron-hole pairs (EHP) generated in this process cause the holes to move to the P-Well, which increases the potential of the P-Well. The elevated potential of the P-Well then creates a forward bias condition with the N+ connected to the Cathode, activating the parasitic NPN BJT. Therefore, the conventional GGNMOS operates by activating the parasitic NPN BJT, providing a discharge path for the ESD surge.

Fig. 1(b) shows a cross-sectional view of the STNMOS (Substrate-Triggered NMOS) structure. The anode is connected to the N+ region of M1 as well as the emitter and base of the PNP BJT, while the collector of the PNP BJT is connected to the P+ region of M1. The cathode is connected to both the N+ region and the gate of M1. STNMOS utilizes substrate-trigger technology to achieve a lower trigger voltage compared to conventional GGNMOS.

The operation principle of the STNMOS is as follows. In the normal state without an ESD event, the STNMOS does not conduct discharge current due to reverse bias. However, when an ESD event occurs and an ESD surge is introduced at the anode, the potential of M1's N+ region and the N-Well of the PNP BJT begins to rise. As the ESD surge continues, the voltage eventually reaches a critical point, causing avalanche breakdown at the junction between the N-Well and the P+ region of the PNP BJT, which generates electron-hole pairs (EHPs). Among these, the holes move toward the P+ region, increasing the potential and turning on the PNP BJT. The operation of the PNP BJT results in current flowing through the collector, which supplies current to the base region of the internal parasitic NPN BJT within M1, thereby assisting in turning on M1. As a result, both the PNP BJT and M1 operate together to provide a discharge path for the ESD surge.

Fig. 2 shows the cross-sectional view of the proposed ESD protection circuit structure. In the proposed ESD protection circuit, the Gate electrode connected to the Cathode is linked to the PNP BJT to prevent leakage current flowing through the Gate, which is present in the conventional STNMOS structure. Additionally, a P+ region is added next to the N+ region connected to the Anode to lower the trigger voltage. The operation principle of the proposed ESD protection circuit is as follows. In the normal state, when no ESD event occurs, the proposed ESD protection circuit remains inactive due to the reverse bias and does not discharge the ESD current. When an ESD event occurs and the ESD surge enters the Anode terminal, the potential of the N+ region of M2 and the N-WELL of the PNP BJT rises. As the ESD surge continues to enter, the potential increases progressively, and when it reaches the threshold, Avalanche breakdown occurs at the junction between the N-Well of the PNP BJT and the P+ region, generating electron-hole pairs (EHP).

Among the generated EHP, the holes move to the P+ region, increasing its potential and turning on the PNP BJT. The operation of the PNP BJT causes the current flowing to the Collector to supply current to the Base region of the parasitic NPN BJT inside M2, helping to turn on M2. As a result, the proposed ESD protection circuit operates by turning on both the PNP BJT and M2, providing a discharge path for the ESD surge.

Fig. 1. Cross section of conventional (a) GGNMOS (gate-grounded NMOS), (b) STNMOS (substrate triggered NMOS).

Fig. 2. Proposed ESD protection circuit.

Fig. 3. The equivalent circuit of the proposed ESD protection circuit.

Fig. 4. The movement of electrons and holes after the generation of electron-hole pairs (EHP).

Fig. 5. (a) Top view. (b) Layout of the proposed ESD protection device.

III. RESULTS AND DISCUSSION

1. TLP Measurement

Fig. 6 shows the TLP measurement results of GGNMOS, STNMOS, and the proposed ESD protection circuit. The proposed ESD protection circuit is designed using the DB 4H-SiC process. The trigger voltage of the proposed ESD protection circuit is 60.7 V, which is lower than that of GGNMOS and STNMOS. This is because the additional P+ inserted into M2 induces an avalanche breakdown at a lower voltage in an ESD event compared to conventional GGNMOS and STNMOS. Additionally, the PNP BJT connected to M2 supplies current to the P-Body region of M2, assisting the operation of the parasitic NPN BJT in M2, thereby resulting in a lower trigger voltage. Therefore, the proposed ESD protection circuit has a lower trigger voltage than the two mentioned ESD protection circuits. The holding voltage of the proposed ESD protection circuit is 27.6 V. Unlike GGNMOS, which operates with only a parasitic NPN BJT, the proposed ESD protection circuit has both M2 and the PNP BJT operating together, providing higher current-driving capability. This enhanced current-driving capability also contributes to the reduction of the on-resistance of the proposed ESD protection circuit.

Fig. 6. TLP measurement of the conventional GGNMOS, STNMOS and the proposed ESD protection device.

Table 1. Summary of the electrical characteristics of the conventional GGNMOS, STNMOS and the proposed ESD protection circuit.

Structure	Trigger Voltage (Vt1)	Holding Voltage (Vh)	2nd Breakdown Current (It2)
GGNMOS	93.9 V	63.8 V	2.4 A
STNMOS	69.9 V	27.4 V	4.2 A
The proposed	60.7 V	27.6 V	4.4 A

2. TLP Measurement Results According to Changes in Design Parameter D1

Fig. 7 shows the TLP measurement results according to the D1 parameter. Unlike the conventional GGNMOS and STNMOS, the proposed ESD protection circuit exhibits a lower trigger voltage because the avalanche breakdown occurs at the N+ and P+ junction when an ESD surge enters the anode terminal. According to Fig. 6, when D1 is 0 $\mu$m, the trigger voltage is the lowest, and as the D1 length increases, the trigger voltage also increases. This is because, as the distance between the N+ and P+ regions increases, the gap between the conduction band and the valence band at the N+/P+ junction widens in the energy band diagram, causing the avalanche breakdown to occur in the P-Body rather than in the P+ region as it did initially.

Fig. 7. TLP measurement of the proposed ESD protection device with changes in design parameters.

Table 2. Electrical characteristics according to changes in design parameter D1.

Design Parameter[um]		Vt1 [V]	Vh [V]
D1	0	60.7	27.6
	2	63.3	27.9
	4	68.9	28.2
	10	80.3	28.9

3. TLP Measurement According to Temperature Variations

Fig. 8 presents the results of the temperature reliability test for the proposed ESD protection circuit, showing its electrical characteristics within the temperature range of 300 K to 425 K. In this experiment, the wafer was heated using a hot chuck control system, and the I-V characteristics were measured using a TLP system. The results indicate that the proposed ESD protection circuit maintains a nearly constant operating voltage despite variations in temperature. This stable behavior is attributed to the material advantages of 4H-SiC, including its wide bandgap, high thermal stability, and low on-resistance.

Fig. 8. Temperature characteristics of the proposed ESD protection device.

IV. CONCLUSION

In this paper, a new structure is proposed to improve the wide snapback characteristics of 4H-SiC-based ESD protection circuits. The proposed ESD protection circuit enhances snapback characteristics by adding a PNP BJT to the conventional GGNMOS to control the trigger voltage and incorporating a P+ region to induce a lower trigger voltage compared to conventional ESD protection circuits. Additionally, to prevent leakage current flowing into the Gate in the existing STNMOS, the Gate is connected to the PNP BJT. TLP measurement results confirm that the proposed ESD protection circuit operates at a lower voltage and exhibits improved on-resistance characteristics compared to conventional ESD protection circuits. Furthermore, by analyzing the impact of the design parameter D1 on the electrical characteristics of the proposed ESD protection circuit, it was observed that as the length of D1 increases, the trigger voltage also increases. The proposed ESD protection circuit is expected to be suitable for high-voltage applications.