LeeYonghwan1,*
JoSengjun1,*
KwonKuduck1
-
(Department of Electronics Engineering and Department of BIT Medical Convergence, Kangwon
National University, Chuncheon 24341, South Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
802.11be, Wi-Fi 7, balanced load, balun-LNA, broadband, current-bleeding, differential current balancer, gm-boosting, local feedback
I. INTRODUCTION
The IEEE 802.11be standard, commonly known as Wi-Fi 7, has been introduced to address
the increasing demand for higher data rates and enhanced network capacity in wireless
communication. By supporting channel bandwidths up to 320 MHz and employing higher-order
modulation schemes, such as 4096-quadrature amplitude modulation (4K-QAM), Wi-Fi 7
significantly improves spectral efficiency and overall throughput. Research on Wi-Fi
transceivers is actively being conducted [1-8]. A key challenge in Wi-Fi 7 transceivers is maintaining a low error vector magnitude
(EVM) while operating at frequencies up to 7.125 GHz. The IEEE 802.11be standard specifies
an EVM requirement of -38 dB for 4K-QAM, but in practical scenarios, a more stringent
target of $<-43$ dB is often desirable to provide a 5 dB margin for robust performance.
To achieve this, the integrated phase noise of the local oscillator (LO) chain must
be lower than -48 dBc, while the nonlinearity components of both receiver (RX) and
transmitter (TX) should be at least -50 dBc. Furthermore, RX and TX noise characteristics
must be carefully optimized to minimize overall system degradation.
The RX for Wi-Fi 7 must support not only the existing 2.4 GHz band (2.4-2.4845 GHz)
and 5 GHz band (5.15-5.85 GHz) but also the 6 GHz band (5.925-7.125 GHz) to ensure
full compatibility with the latest standards. To achieve this, a low-noise amplifier
(LNA) with wideband coverage from 5.15 GHz to 7.125 GHz is required to support both
the 5 GHz and 6 GHz bands effectively. Additionally, meeting the stringent EVM specifications
demands an LNA with both low-noise and high-linearity characteristics to minimize
signal degradation and maintain modulation accuracy. Since reducing system complexity
is crucial in modern Wi-Fi designs, a single-ended input is preferred to minimize
the number of required input pins. However, single-ended input LNAs are inherently
less advantageous than balanced architectures in terms of signal-to-noise ratio (SNR),
common-mode rejection ratio, and power supply rejection ratio. Balanced architectures
provide superior noise performance and lower second-order nonlinearity, making single-ended-to-differential
conversion an essential function in many LNA designs. On-chip passive baluns can facilitate
this conversion but suffer from high insertion loss, which degrades the noise figure
(NF) of the RX. Active baluns offer an alternative by performing the conversion without
significantly compromising NF, but this comes at the cost of increased power consumption.
Existing studies have proposed balun-LNA architectures that employ noise-cancelling
techniques with single-ended-to-differential conversion [9-16]. However, many of these designs suffer from imbalanced output loads [9,10].
This paper proposes a new noise-cancelling common-gate (CG)-common-source (CS) balun-LNA
architecture designed for low-power and low-voltage applications in Wi-Fi 7 systems.
The proposed balun-LNA employs local feedback transconductance ($g_{m}$)-boosting
techniques for the CG stage and a current-reuse inverter-type amplifier for the CS
stage to achieve low noise performance with low-power consumption. Section II reviews
previous noise-cancelling LNA topologies. The proposed noise-cancelling CS-CS balun-LNA
is introduced and analyzed in Section III. Section IV presents the simulation results,
and Section V concludes the study.
II. REVIEW OF PREVIOUS NOISE-CANCELLING LNA TOPOLOGIES
Over the past few decades, various LNA topologies have been extensively studied to
achieve low noise and high linearity [9-16]. The topologies can be broadly divided into two categories, which are CG-CS noise-cancelling
LNAs and LNAs with feedback. In the design of the LNA, input matching, NF, and linearity
are considered as key performance metrics. Among these, NF is the most important parameter
because it determines the sensitivity of the RX. This section provides a brief overview
of the previous state-of-the art of the active balun-LNA and noise-cancelling single-ended
LNA considering these parameters.
1. CG-CS Noise-Cancelling Balun-LNA
Fig. 1(a) illustrates the basic CG-CS noise-cancelling balun-LNA structure. In this configuration,
$M_1$ determines the input impedance for power matching, while $M_{2}$ cancels the
noise and distortion introduced by $M_{1}$ at the LNA output when both the CG and
CS stages have the same voltage gain [9]. Although the basic CG-CS balun topology offers the advantage of noise cancellation
without additional components, it typically exhibits a NF exceeding 3 dB. To achieve
a lower NF, it is essential to reduce the noise contribution from $M_{2}$. One approach
to address this issue is presented in Fig. 1(b), where the $g_{m}$ of the CS stage is scaled up by a factor of ${N}$ relative to
the CG stage, and the load resistor of the CS stage is scaled down by the same factor
[10]. This configuration allows the practical CG-CS balun topology to achieve a lower
NF than the basic CG-CS balun topology when both stages have the same voltage gain.
However, the asymmetric load at the output can cause differential imbalance when random
mismatches occur, which degrades noise cancellation and increases second-order nonlinearities
in the following stage. To address this problem, a current-bleeding (CBLD) circuit
is employed in the 1: ${N}$ CG-CS balun-LNA structure shown in Fig. 1(c) [11]. By setting the $g_{m}$ ratio of CBLD transistor ($M_{5}$) to (${N}-1$), the bias
current of the CS stage is divided between $M_{5}$ and $M_{4}$ in a 1: (${N}-1$) ratio.
This current bleeding ensures equal current flow through each load resistor, which
provides symmetric loads, enhances noise cancellation, and maintains linearity. However,
this structure is not suitable for low-power, low-voltage applications due to higher
power consumption [11]. To reduce power consumption, a balun-LNA with local feedback $g_m$-boosting technique
was proposed and shown in Fig. 1(d) [12]. This feedback increases the overall $g_m$ of the CG stage by the loop gain, thereby
achieving both low power consumption and a reduced NF. However, it still suffers from
relatively high power consumption. The conventional CG-CS balun-LNAs shown in Fig. 1(a)-(d) are not effective to support the 5 GHz and 6 GHz bands of Wi-Fi 7 because of
limited 3dB bandwidth. The balun-LNA, as shown in Fig. 1(e), employs broadband $g_m$-boosting technique, where the $g_m$s of both the amplifier
and the CG stage are simultaneously adjusted to control gain and impedance while maintaining
a wide frequency range. Additionally, a dual-path noise cancellation technique effectively
suppresses noise over a broad bandwidth while minimizing silicon area. However, it
still exhibits a relatively high NF of 6.8 dB [13].
Fig. 1. Conventional noise-cancelling LNA topologies: (a) basic CG-CS balun-LNA [9] (b) practical CG-CS balun-LNA [10] (c) CG-CS balun-LNA with current-bleeding circuit [11] (d) CG-CS balun-LNA with local feedback $g_m$-boosting technique and balanced loads
[12] (e) balun-LNA with dual-path noise-canceling technique [13] (f) CG-CS LNA with resistor and source follower feedback [14] (g) CG-CS LNA with active feedforward path [15] (h) CG-CS LNA with active feedforward and passive network [16].
2. Broadband Noise-Cancelling LNA
Extensive studies have been conducted to achieve broadband operation in LNAs [14-16]. Fig. 1(f) shows a broadband noise-cancelling CG-CS LNA using resistor and source follower feedback
[14]. The source follower feedback forms a shunt load at the gate of the input-matching
transistor. This modification allows for a larger feedback resistor, improving broadband
characteristics while enhancing gain and NF. However, this structure still exhibits
a relatively high NF exceeding 3.7 dB. Fig. 1(g) presents a broadband active feedforward CG-CS LNA with a current-mode combining network
[15]. Here, an active feedforward stage ($M_1$ and $R_L$) in the main path enhances $g_m$
and reduces power consumption, ensuring stable operation over a wide frequency range.
Additionally, noise is canceled via the auxiliary path (CS amplifier $M_2$), with
signals directly combined in the current-mode combining network ($M_4$ and $M_5$).
Meanwhile, $M_6$ operates as a CBLD circuit to maintain consistent high-frequency
performance. However, $M_6$ introduces additional noise, degrading overall noise performance.
To mitigate this issue, the LNA, as shown in Fig. 1(h), has a passive network, where ${C}$ acts as an AC ground at high frequencies, directing
the noise current of $M_6$ to AC ground and effectively filtering it out [16]. Additionally, passive peaking extends the bandwidth. However, the added passive
network increases silicon area overhead.
Proposed CG-CS Balun-LNA Employing Local Feedback $g_{m}$-Boosting And Current-Bleeding
Technique
This section presents a new low-power noise-canceling CG-CS balun-LNA topology that
employs local feedback $g_m$-boosting and CBLD technique. The schematic of the proposed
balun-LNA is shown in Fig. 2(a). In conventional CG-CS balun-LNAs, the main transistor in the CS stage contributes
significantly to the overall noise of the balun-LNA. To address this issue, the proposed
design utilizes a current-reuse inverter-type amplifier as the CS stage. This inverter-type
amplifier enhances the overall $g_m$ of the CS stage, thereby improving the NF of
the balun-LNA through the current-reuse technique. Additionally, $M_{2P}$ in the inverter-type
amplifier also functions as a CBLD circuit. As a result, the DC current flowing into
the cascode stage ($M_4$) is equal to that of $M_3$, allowing the use of a balanced
load at the differential output. Furthermore, the cross-coupled cascode stage ($M_{3,4}$
and $C_{C1,2}$) acts as a differential current balancer (DCB), enhancing both gain
and phase balance. In addition, the output of the CS stage is connected to the gate
of $M_1$ via $C_{FB}$, forming a local negative feedback loop. This negative feedback
increases the $g_m$ of the CG stage by the loop gain, thereby reducing the required
$g_m$ of the CG transistor for input power matching with the source resistance $R_{S}$.
Consequently, this approach significantly reduces power consumption of the balun-LNA.
Fig. 2. Proposed noise-cancelling CG-CS balun-LNA: (a) schematic (b) small-signal
equivalent circuit.
1. Voltage Gain and Input Impedance
The small-signal equivalent circuit of the proposed balun-LNA, shown in Fig. 2(b), is analyzed to derive the voltage gain and input impedance. For simplicity, the
effect of channel-length modulation is neglected. Additionally, the impedances of
$C_{C1}$ and $C_{C2}$ are assumed to be negligible at the operating frequency, and
the $g_m$ of the CG stage is assumed to be equal to that of the cascode transistors
($M_4$ and $M_5$). By analyzing the small-signal model with Kirchhoff current law
(KCL) and Kirchhoff voltage law (KVL), the voltage gain and input impedance of the
proposed balun-LNA can be derived as follows:
where $g_{m2N}$ and $g_{m2P}$ denote $g_m$ of $M_{2N}$ and $M_{2P}$, respectively.
$R_{P}$ is the resistance of the parallel ${LC}$ tank at the resonant frequency, and
$A_{OL}$ is the open-loop gain of the local feedback, given to $A_{OL} = (g_{m 2N}
+ g_{m 2P})/g_{m1}$, where $g_{m1}$ is $g_m$ of $M_1$. Table 1 presents the hand-calculated and simulated input impedance of the proposed balun-LNA.
It can be observed that the hand-calculated result closely matches the simulation
result. When the input impedance matching condition of $1/(g_{m1} (1+A_{OL})) = R_{S}$
is satisfied, the voltage gain can be expressed to
Table 1. Input impedance of the proposed balun-LNA.
|
Parameters
|
Hand Calculation
|
Simulation
|
|
RIN [Ω]
|
22
|
26
|
2. Noise Analysis
All noise sources are assumed to be uncorrelated. For an intuitive analysis, the NF
is derived by neglecting the parasitic capacitances. To simplify the derivation further,
the body effect is also disregarded. When a voltage source $V_{S}$ with a source resistance
$R_{S}$ is applied to the source of $M_1$, the total noise factor of the proposed
balun-LNA can be expressed to
where ${EF}$ represents the excess noise factor, which quantifies the contribution
of each device to the overall noise factor $F$, $k$ is Boltzmann's constant, ${T}$
denotes the absolute temperature. $V^{2}_{M1}$, $V^{2}_{M2N}$, $V^{2}_{M 2P}$, $V^{2}_{M3}$,
$V^{2}_{M4}$, and $V^{2}_{RP}$ represents the output-referred noise voltage generated
by $M_{1}$, $M_{2N}$, $M_{2P}$, $M_{3}$, $M_{4}$, and $M_{2P}$, respectively [12]. To simplify the analysis, channel-length modulation is neglected, and it is assumed
that $g_{m1} = g_{m 3} = g_{m4} = g_m$. The noise factor of $M_1$ is assumed to be
canceled based on the noise-canceling theory. Because the noise contributions of $M_1$
and $R_{p}$ are small enough, these can be neglected from the overall noise factor
of the proposed balun-LNA. By applying simple network analysis with the superposition
method and KCL/KVL, each noise source is considered individually by shorting or opening
resithe others. Under input impedance matching conditions, the resulting excess noise
factors can be derived as follows:
Here, $\gamma$ is the noise parameter. Therefore, the noise factor of the proposed
balun-LNA can be expressed by
From (5)-(8), it is evident that $EF_{M2N}$ and $EF_{M 2P}$ are the dominant excess noise factors
determining the overall ${F}$. Thus, minimizing these values is essential to achieve
a low NF. Although increasing $g_{m 2N}$ and $g_{m 2P}$ can reduce the overall NF,
the matching impedance is determined by $g_{m 2N}$ and $g_{m 2P}$. Therefore, the
design must achieve a low NF while satisfying the S11 specification. Table 2 presents the hand-calculated and simulated noise contributions of the proposed balun-LNA.
It can be observed that the hand-calculated results closely match the simulation results.
As expected, the noise contributions from $EF_{M2N}$ and $EF_{M2P}$ are the highest.
Table 2. Noise contributions of the proposed balun-LNA.
|
Parameters
|
Hand Calculation
|
Simulation
|
|
EFM2N
|
0.384
|
0.37
|
|
EFM2P
|
0.256
|
0.24
|
|
EFM3
|
0.102
|
0.11
|
|
EFM4
|
0.102
|
0.11
|
|
ETC
|
0.02
|
0.05
|
|
F
|
1.864
|
1.88
|
|
NF [dB]
|
2.7
|
2.74
|
IV. SIMULATION RESULTS
The proposed noise-cancelling CG-CS balun-LNA with local feedback $g_m$-boosting and
CBLD technique for Wi-Fi 7 applications was designed using a 28-nm CMOS process. The
layout of the balun-LNA is depicted in Fig. 3. The active die area, excluding the bond pads, occupies 0.079 mm$^2$. To verify the
performance of the designed balun-LNA, post-layout simulations were performed. It
draws a current of 3.5 mA at a supply voltage of 0.8 V. The simulated S11 performance
is shown in Fig. 4, demonstrating that the balun-LNA achieves an S11 value of less than $-10$ dB across
the frequency range of 5 to 7 GHz. Fig. 5 illustrates the voltage gain of the balun-LNA, which exceeds 23 dB. Fig. 6 presents the NF performance of the proposed balun-LNA, with the NF ranging from 2.74
to 3.1 dB. Fig. 7 presents simulated input-referred third-order intercept point (IIP3) and output-referred
third-order intercept point (OIP3). The two-tone test conditions for the IIP3 are
$f_{1} = f_{IMD3} + 10$ MHz, $f_{2} = f_{IMD3} + 20$ MHz and $P_{f1} = P_{f2} = -50$
dBm, where $f_{IMD3}$ is the third-order intermodulation distortion (IMD3) frequency.
The simulated IIP3 and OIP3 reach maximum values of $-4.48$ dBm and $17.86$ dBm, respectively.
Table 3 summarizes and compares the performance of the proposed balun-LNA with previous works.
For a fair performance comparison, the following figure-of-merit (FOM) is used.
where, BW is the operating frequency ranges ($f_{max} - f_{min}$), $F_{min}$ is the
minimum noise factor, and $P_{dc}$ is the DC power consumption. As shown in Table 3, the proposed balun-LNA achieves a low NF while maintaining low power consumption
and a compact die area. Notably, it supports a wide frequency range while maintaining
a high voltage gain.
Fig. 3. Layout of the proposed balun-LNA.
Fig. 5. Simulated voltage gain.
Fig. 7. Simulated IIP3 and OIP3.
Table 3. Performance summaries of the proposed balun-LNA and comparison with previous
state-of-the-art works.
|
References
|
JSSC2008
[10]
|
TCASI2019
[11]
|
TCASI2020
[12]
|
TMTT2025
[13]
|
TCASII2019
[14]
|
TMTT2021
[15]
|
TCASII2022
[16]
|
This
work$\dagger$
|
|
Process
|
65-nm CMOS
|
65-nm CMOS
|
65-nm CMOS
|
65-nm CMOS
|
65-nm CMOS
|
40-nm CMOS
|
40-nm CMOS
|
28-nm CMOS
|
|
Topology
|
CG-CS LNA
|
CG-CS LNA + modified CBLD circuit
|
CG-CS LNA + local FB + modified CBLD
|
CG-CS LNA +
gm-boost based
|
CG-CS LNA + resistor and source follower FB
|
CG-CS LNA + active feedforward
path
|
CG-CS LNA + passive network
|
CG-CS LNA +
local FB gm-boosting + current-bleeding
|
|
Frequency range [GHz]
|
0.2-5.2
|
0.05-1
|
0.05-1.32)
|
0.1-4.3
|
0.5-7
|
1-11
|
2-12
|
4.8-7.2
|
|
Balun function
|
YES
|
YES
|
YES
|
YES
|
NO
|
NO
|
NO
|
YES
|
|
S11 [dB]
|
<-10
|
<-10
|
<-10
|
<-8.2
|
<-10
|
<-10
|
<-10
|
<-10
|
|
Voltage gain [dB]
|
13-15.6
|
24-30
|
24-27.5
|
4.1-20
|
16.8
|
14-17
|
16.5-19.5
|
23.6-24.6
|
|
NF [dB]
|
2.9-3.5
|
2.3-3.32)
|
2.3-32)
|
1.8-6.2
|
2.87-3.77
|
3.5-5.5
|
3.2-5.2
|
2.74-3.1
|
|
IIP3/OIP31) [dBm]
|
0/15.6
|
-4.1/25.9
|
-2.2/25.3
|
-5.3-6.2/
8.7-16.9
|
-4.5/12.3
|
-2.8/14.2
|
-3.5/16
|
-4.84/17.86
|
|
Power [mW]
|
21
|
19.8
|
5.7
|
2.1-7.6
|
11.3
|
9
|
9
|
2.8
|
|
Supply [V]
|
1.2
|
2.2
|
1
|
NA
|
1.2
|
1.2
|
1.2
|
0.8
|
|
Area [mm2]
|
0.01
|
0.0448
|
0.046
|
0.002
|
0.044
|
0.061
|
0.092
|
0.079
|
|
FOM
|
9.59
|
14.27
|
19.21
|
15.01
|
10.18
|
13.72
|
16.08
|
19.26
|
1)OIP3 = IIP3 + voltage gain
2) NF with the measurement buffer
$*$NA: not available
$\dagger$post-layout simulation result
V. CONCLUSION
The proposed 4.8-7.2 GHz broadband low-power noise-canceling CG-CS balun-LNA is
designed to meet the performance demands of Wi-Fi 7 transceivers. By employing local
feedback $g_m$-boosting and CBLD techniques, it effectively enhances $g_m$ while maintaining
low power consumption. The CBLD approach also ensures differential output balance,
addressing gain and phase mismatch issues. As a result, the proposed balun-LNA achieves
broadband operation, low noise, and energy efficiency, making it a highly suitable
solution for Wi-Fi 7 applications.
ACKNOWLEDGMENTS
This work was supported by the National Research Foundation of Korea(NRF) grant
funded by the Korea government(MSIT) (No. 2023R1A2C1003227, RS-2023-00221494, and
RS-2025-02216989). The EDA tool was supported by the IC Design Education Center (IDEC),
South Korea.
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Yonghwan Lee received his B.S. and M.S. degrees in electronics engineering from
Kangwon National University, Chuncheon, Korea, in 2023 and 2025, respectively. His
research interests include CMOS mmWave/RF/analog integrated circuits and RF system
design for wireless communications.
Sengjun Jo received his integrated B.S. and M.S. degree from the Department of
Electronics Engineering, Kangwon National University, Chuncheon, South Korea, in 2024,
where he is currently pursuing a Ph.D. degree with the Department of Electronics Engineering.
His research interests include CMOS mmWave/ RF/analog integrated circuits and RF system
design for wireless communications. He focuses on studying an IIP2-calibration-free
blocker-tolerant receiver architecture and channel-selection LNAs for advanced cellular
applications. He was a recipient of a Korean Intellectual Property Office (KIPO) Commissioner
Award for Korea Semiconductor Design Competition in 2021.
Kuduck Kwon received his B.S. and Ph.D. degrees in electrical engineering and computer
science from Korea Advanced Institute of Science and Technology (KAIST), in Daejeon,
Korea, in 2004 and 2009, respectively. His doctoral research concerned digital TV
tuners and dedicated short-range communication (DSRC) systems.
From 2009 to 2010, he was a Post-Doctoral Researcher with KAIST, where he studied
a surface acoustic wave (SAW)-less receiver architectures and developed 5.8GHz RF
transceivers for DSRC applications. From 2010 to 2014, he was a Senior Engineer with
Samsung Electronics Co. LTD., Suwon, South Korea, where he has been involved with
studies of the SAW-less software-defined receivers and development of CMOS transceivers
for 2G/3G/4G cellular applications and receivers for universal silicon tuners. In
2014, he joined the Department of Electronics Engineering, Kangwon National University,
Chuncheon, South Korea, where he is currently a Professor. His research interests
include CMOS mmWave/RF/analog integrated circuits and RF system design for wireless
communications.