P BBhuvana 1
APrathiba2
S VKanchana Bhaaskaran3
-
(Department of Electronics and Communication Engineering, Sathyabama Institute of Science
and Technology, Chennai, Tamil Nadu 600119, India)
-
(Center for Nanoelectronics and VLSI design & School of electronics engineering, VIT
Chennai, Chennai, Tamil Nadu)
-
(Vice Chancellor, VIT, Tamil Nadu, India)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Adiabatic logic, differential power analysis, FinFETs, S-box
I. INTRODUCTION
Emergence of Internet of Things (IoT) has led to increased use of digital business
solutions such as e-commerce, internet banking, secure e-mail communications and financial
transactions among a plethora of applications. Smart cards and RFID (Radio Frequency
IDentification) tags are employed in majority of digital applications, where security
of information processed is considered to be quintessential. Information security
is based on the embedded cryptographic algorithms in those particular applications.
Hence, secured implementations demand major consideration in security architectures.
Implementation attack or Side Channel Attack (SCA) is an attack that identifies the
secured information by real time monitoring of electronic devices. These attacks extract
information about power consumption, timing and electromagnetic radiation from the
device on which the attack are executed. Such attacks can be either active or passive.
Active attack can either alter the system activity or affect its performance. Passive
attacks will not disrupt the process involved and it is more dangerous than the active
attacks. SCA are passive type of attacks and hence they gain increasing significance
among the researchers [1-3].
Adiabatic logic design is a non-conventional low power circuit design technique which
employs the principle of charge recovery. The charge spent by the power source (aka
power clock source, since the source acts as a timing clock also) during the switching
of a node is retrieved by the power clock source after the switching information is
passed on to the next stage. As a major portion of charge is recovered back by the
power clock source, the total energy consumption of adiabatic logic circuit happens
to be lower than that of the conventional CMOS (Complementary Metal Oxide Semiconductor)
logic circuit. Generally, energy consumption in conventional CMOS can be reduced by
limiting any one of the following factors, viz., i) Supply voltage, ii) Load capacitance
and iii) Number of input transitions. Curtailing the supply voltage decreases the
energy consumption quadratically to a greater extent. However, the performance of
the system is bound to be degraded. In contrast, adiabatic logic circuits utilise
a ramp power clock which does not abruptly switch from 0 to V${}_{\rm DD}$ [4,5]. Fig. 1 depicts the adiabatic switching principle, where PC represents power clock signal,
F and /F represents the functional and complementary functional block [6-11].
Fig. 1. Adiabatic switching principle.
Adiabatic logic circuits found in literature operate on two phase or four phase power
clock sources majorly [12,13]. Power clock source employed in this proposed circuit design is a four-phase trapezoidal
power clock source. Additionally, the uniform power dissipation incurred by an adiabatic
circuit makes it an attractive choice for the side channel attack resistant circuit
designs [14]. Energy dissipated in an adiabatic logic circuit is given by
where C${}_{\rm L}$ is the load capacitance, T is the time period, R is the parasitic
resistance of the charging pFinFET device and V${}_{\rm DD}$ is the power clock peak
voltage. One complete cycle consists of charging and recovery. Recovery process will
also dissipate equal amount of energy. Hence, the total energy dissipated in adiabatic
logic is given by
From above equation, it is clear that slower the power clock ramp rate and ramp clock
frequency, lesser is the energy consumed [15,16].
In this paper, the efficiency of FinFET based Positive Feedback Symmetric Adiabatic
Logic is validated by the design of 4-bit multiplicative inverse architecture based
on finite fields. Inversion is the most important design component whose efficient
implementation leads to performance enhancement in the AES S-box architecture [1-3]. FinFET based PFSAL circuits realise lower leakage currents and reduced non-adiabatic
energy loss when compared to the existing FinFET based CSSAL [17], EESPFAL [18], SQAL [19], and FinSAL [20] type of adiabatic logic circuits. Energy efficiency has been validated in different
operating frequencies additionally. Normalized energy deviation (NED) and normalized
standard deviation (NSD) of all above said circuits have been calculated and analyzed
to highlight the security characteristics of the proposed circuit.
The authors in their earlier work [21] discussed designing the PRESENT 8-bit S-box into use via current adiabatic logic
families, which include PFAL, SQAL, CSSAL, and FinSAL. A new adiabatic logic family
with a name positive feedback symmetric adiabatic logic (PFSAL) is presented in this
paper. The most significant change of the implementations is in contrast to the previous
designs, passive capacitive output storage of the previous families is abandoned in
favor of actively controlled discharge FinFETs, a change which improves both energy
recovery and uniformity of power consumption levels. Such architectural modifications
enhance performance rates significantly, including power efficiency and side-channel
vulnerability.
This paper is organized as follows: Section II briefs the topologies of secure adiabatic
logic circuit designs. Section III describes the operation of FinFET based PFSAL,
basic logic circuits designed using PFSAL. Section IV presents the functioning of
the FinFET device and analysis of PFSAL circuit for possible variations of FinFET
parameters. Section V analyses the simulation results of PA resistant adiabatic logic
circuits under consideration and the article is concluded in Section VI.
II. TOPOLOGY OF SECURE ADIABATIC LOGIC CIRCUITS
Adiabatic logic methodology can be utilized for the design of cryptographic circuits
as these circuits are capable of consuming uniform current and unvarying power traces
irrespective of the input transitions. Some of the commonly used secure adiabatic
logic circuits are secure adiabatic logic (SAL) [18], Symmetric Adiabatic Logic (SyAL) [20], SQAL, CSSAL, symmetric pass gate adiabatic logic (SPGAL) [21], FinSAL, EE-SPFAL, without charge sharing quasi adiabatic logic (WCS-QuAL) [23], and adiabatic logic with single charge sharing transistor [24]. Fig. 2 illustrates some of the commonly used Secure adiabatic logic inverter/buffer circuits.
Fig. 3 depicts the supply current traces of conventional CMOS based inverter designed using
MOSFET and FinFET devices and, supply current traces of the adiabatic inverter. 32nm
MOSFET is used for the design of conventional CMOS design, which has a peak current
of 11 $\mu$A. it may be noted that supply peak current of FinFET based conventional
inverter design is only 1.5 $\mu$A. Adiabatic logic circuit designed using FinFETs
incurs very low peak current below 1 $\mu$A. As shown in the figure, the circuit design
using FinFET based adiabatic logic consumes lower current and it also does not incur
any peak current spikes as in CMOS circuits.
Fig. 2. Secure adiabatic logic inverter/buffer circuits (a) SQAL, (b) FinSAL, (c)
CSSAL, and (d) EE-SPFAL.
Fig. 3. Current traces of conventional and adiabatic inverter.
III. DESIGN AND ANALYSIS OF POSITIVE FEEDBACK SYMMETRIC ADIABATIC LOGIC
1. Operation of PFSAL
Some of the significant attributes of PFSAL circuits are as follows [22]:
1. Reduced leakage current.
2. Decreased trapped charge in the output nodal capacitances.
3. Employs differential cascode structure.
4. Existence of discharge FinFETs, which helps in recovering the trapped charges
from output nodal capacitances.
5. Elimination of diodes.
6. Generates uniform current and power traces for any input change.
7. Operates efficiently across a wider range of frequency from 100KHz to 1GHz.
Consider IN - /IN as the input and complimentary inputs to the PFSAL circuit and OUT
- /OUT the corresponding output and its complimentary outputs. Logic structure of
PFSAL is shown in Fig. 4a. Functional and complementary functional blocks can be substituted for required logic
as represented in dotted lines by FinFETs FN1 and FN2, for the case of an inverter.
PFSAL is powered by four-phase power clock source. The input-output transients of
PFSAL is depicted in Fig. 4b.
Fig. 4. (a) Logic structure and (b) input output transients of PFSAL.
1.1 Wait and discharge phase (T1)
During the wait phase (T1), power clocks PC1 and PC3 remain stable at 0V and V${}_{\rm
DD}$, respectively. The device FN5 is enabled as PC3 remains at peak voltage V${}_{\rm
DD}$. Input IN starts to ramp from 0V to V${}_{\rm DD}$ and /IN remains at 0V. Input
IN ramps up to V${}_{\rm DD}$ and when the gate to source voltage of nFinFET becomes
greater than the threshold voltage, FN1 is enabled. At this instinct, current flow
through device FN1 is zero, as the source and drain of the device are at ground. Discharge
signal DIS is enabled in this phase, which enables devices FN3 and FN4. The node /OUT
establishes a path to the ground. Any unclaimed charge stored in the output nodal
capacitances find a path to the ground through the devices FN3 and FN5.
1.2 Evaluation pahse (T2)
During the evaluation phase (T2), power clock PC1 ramps up to V${}_{\rm DD}$ from
ground and PC3 inclines from peak voltage down to 0V. DIS is disabled in this phase,
which disables the nFinFETs FN3 and FN4 from conduction. When PC3 falls down below
the threshold voltage of FN5, it is switched OFF. As FN1 is switched ON, node /OUT
is directly connected to power clock source and /OUT node follows power clock source.
At this juncture, node OUT is at LOW voltage, which enables pFinFET FP1 to conduct.
Node /OUT is charged to HIGH state through both FN1 and FP1. The charging path established
is a parallel charging path. This results in lower Ron of the charging path.
1.3 Hold phase (T3)
During the hold phase (T3), the power clock PC1 remains constant at V${}_{\rm DD}$.
In contrast, PC3 remains at 0 V. Additionally, node /OUT is stable at V${}_{\rm DD}$
following the power clock PC1. Input IN falls down to 0 V.
1.4 Recovery phase (T4)
During the recovery phase (T4), the power clock PC1 ramps down to 0V. Input IN is
constant at 0V, which in turn disables nFinFET FN1. The voltage at node /OUT is higher
than the voltage at PC1. Hence, the charge stored in the output nodal capacitances
are recovered by power clock source through FP1. This recovery process continues as
long as the gate to source voltage remains below the threshold voltage of pFinFET
FP1.
2. PFSAL Based AND / NAND Logic Gate
AND / NAND logic circuit designed using PFSAL is shown in Fig. 5(a). Total number of FinFETs used in the design is 13. Consider A, /A, B and /B as inputs
and its complementary inputs, respectively. When A and B remains at V${}_{\rm DD}$,
corresponding FinFETs FN4, FN5, FN6 and FN10 are switched ON. During the evaluation
phase, PC1 ramps up to V${}_{\rm DD}$ and PC3 falls down to 0V. OUT node is connected
to the power clock PC1, through the path formed by FinFETs FN4 and FN5. The LOW voltage
at /OUT node enables the device FP1. Node OUT is charged to logic HIGH through both
the paths established by FinFETs FN4-FN5 and FP1. During the hold phase, OUT node
follows the power clock PC1. During the recovery phase, PC1 ramps down to 0 V. FN4
and FN5 are disabled in this phase, and hence the charge stored in the nodal load
capacitance is recovered by PC1 through FinFET FP1. During the wait phase, when the
discharge pulse is enabled along with power clock PC3, they provide a path for the
trapped charged to flow to ground. Fig. 5(b) shows the input-output transients of all input combinations of AND / NAND logic gate.
Fig. 5(c) depicts the uniform power traces for the combination of 00 $\rightarrow$ 10 $\rightarrow$
11 $\rightarrow$ 11 $\rightarrow$ 10 $\rightarrow$ 00 $\rightarrow$ 01.
Fig. 5. PFSAL based (a) AND/ NAND logic structure, (b) input-output, power clock and
current transients, and (c) uniform power traces.
3. PFSAL Based XOR / XNOR Logic Gate
PFSAL based XOR/ XNOR logic gate is depicted in Fig. 6(a). Consider input A to be at 0 V and B at V${}_{\rm DD}$, the peak voltage. During
the evaluation phase, FinFETs FN4, FN5 and FN8 get switched ON. Node OUT is directly
connected to the power clock source PC1 through the path formed by FN4 and FN5. The
pFinFET FP1 is switched ON, due to the LOW voltage in node /OUT node. The capacitances
in output node OUT is charged through the parallel paths formed by FN4, FN5 and FP1.
During the hold phase, OUT node follows PC1. During the recovery phase, inputs are
switched OFF, which in turn disables FN4 and FN5. Hence, the charge is recovered by
the power clock through FP1. Fig. 6(b) represents the input-output transients, power clocks and discharge signals of PFSAL.
Fig. 6(c) depicts the uniform power traces of PFSAL XOR/ XNOR logic gate for the input combinations
of 00 $\rightarrow$ 10 $\rightarrow$11 $\rightarrow$ 11 $\rightarrow$ 10 $\rightarrow$
00 $\rightarrow$ 01.
Fig. 6. PFSAL based (a) XOR/ XNOR logic structure, (b) input-output, power clock and
current transients, and (c) uniform power traces.
4. Effect of Load Capacitance on PFSAL Logic
This section analyses the reliability parameter of PFSAL logic against PA attack.
The effect of varying load capacitance on power dissipation is analysed. Simulations
have been carried out using BSIMCMG 32nm FinFET models [22]. Simulations are carried out with an output load capacitance of 1fF connected at
the output nodes. Table 1 depicts the FinFET parameters used in the realization of adiabatic logic circuits
considered.
When we consider the practical difficulties that may occur due to manufacturing defects
and routing issues, the output nodal or load capacitances of the circuit may not be
balanced in practice. This can result in decreasing reliability for the design. Effect
of balanced and unbalanced load capacitances on PFSAL logic is discussed in this section.
In the case of balanced load capacitance, both the output capacitances connected at
nodes OUT and /OUT are of value 1 fF. In order to analyse the case of unbalanced load
capacitance, two different cases have been analysed for PFSAL based AND / NAND logic
gate. Case 1 with an output nodal capacitance of 0.5 fF-1 fF and case 2 with load
capacitance of 2 fF-1 fF.
From Table 2, it can be observed that balanced load capacitance based PFSAL AND/NAND logic gate
consumes minimum energy consumption of 0.179fF and a maximum energy consumption of
0.182fF. NED is the parameter which indicates the difference between the minimum and
maximum energy consumption for all probable input combinations in percentage. This
can be represented as $\text{NED}%=(\mathrm{E}_{\max} - \mathrm{E}_{\min})/\mathrm{E}_{\max}$,
where E$_{\max}$ is the maximum energy consumption and E$_{\min}$ is the minimum energy
consumption, respectively. Normalized Standard Deviation (NSD) is the ratio between
the standard deviation and the average energy consumption for all possible input combinations.
It is represented as $\text{NSD}%=\sigma\mathrm{E}/\mathrm{E}_{\rm avg}$, where $\sigma$E
is the standard deviation and E$_{\rm avg}$ is the average energy consumption for
all input combinations. NED and NSD aids in analyzing the DPA resistant properties
of the circuits at cell level. It may be noted that NED% and NSD% is 0.015 and 0.007
for a balanced PFSAL based AND/NAND logic, respectively. Table 3 depicts the effect of balanced and unbalanced load capacitance for PFSAL based XOR/XNOR
logic gate. NED% and NSD% values are observed to be less than 1%. Hence, it can be
inferred that PFSAL based logic gates can be used for design of low power operating
secured IoT devices.
Table 1. Simulation parameters for the baseline.
|
FinFET Parameters
|
Parameter Values
|
|
Gate Length (Lg)
|
30nm
|
|
HFIN
|
5nm
|
|
TFIN
|
10nm
|
|
Effective Oxide Thickness (EOT)
|
1nm
|
|
NFIN
|
1
|
|
Gate Work Function
|
4.61eV
|
Table 2. Effect of balanced and unbalanced load capacitance cases for PFSAL based
AND/NAND logic gate.
|
Freq
(MHz)
|
PFSAL (Balanced)
|
PFSAL (Unbalanced) 0.5fF
|
PFSAL
(Unbalanced) 2fF
|
|
E$_{min}$ (fJ)
|
0.179
|
0.128
|
0.226
|
|
E$_{max}$ (fJ)
|
0.182
|
0.143
|
0.247
|
|
E$_{avg}$ (fJ)
|
0.181
|
0.137
|
0.238
|
|
NED%
|
0.015
|
0.105
|
0.084
|
|
NSD%
|
0.007
|
0.050
|
0.038
|
Table 3. Effect of balanced and unbalanced load capacitance cases for PFSAL based
XOR/XNOR logic gate.
|
Freq
(MHz)
|
PFSAL (Balanced)
|
PFSAL (Unbalanced) 0.5fF
|
PFSAL
(Unbalanced) 2fF
|
|
E$_{min}$ (fJ)
|
0.122
|
0.169
|
0.213
|
|
E$_{max}$ (fJ)
|
0.126
|
0.170
|
0.219
|
|
E$_{avg}$ (fJ)
|
0.124
|
0.169
|
0.216
|
|
NED%
|
0.005
|
0.029
|
0.026
|
|
NSD%
|
0.003
|
0.015
|
0.011
|
IV. BACKGROUND OF FINFETS
FinFET is a non-planar, three dimensional and tri-gated transistor. The structure
of FinFET consists of a thin fin material embedded on a substrate. The channel is
fully wrapped around by the gate of the device, which in effect provides overall control
over the channel [24,25]. While the channel of a MOSFET is oriented in horizontal manner, the channel of FinFET
is vertically oriented [26].
Some of the key advantages of FinFET are i) Lower power consumption, ii) Reduced leakage
current, iii) Reduced short channel effects, iv) Low voltage operation capability
and v) Faster device operation than the conventional CMOS counterparts. The commonly
used operating modes of FinFET are i) Shorted gate mode, ii) Independent gate mode
and iii) Reverse bias mode. In this paper, shorted gate mode is utilised. In shorted
gate mode, the front gate and back gate are tied together leading to a three terminal
device structure. Structure of FinFET is depicted in Fig. 7. Effective width of FinFET depends on the height of the fin (HFIN), Thickness of
the fin (TFIN) and number of fins (NFIN). Width of the fin is normally an integer
multiple of the height of the fin. This feature is normally referred as the width
quantization.
Fig. 7. Structure of FinFET.
V. RESULT AND DISCUSSION
This section analysis the efficiency of FinFET-based PFSAL circuits in comparison
with secure adiabatic logic circuits such as SQAL, CSSAL, FinSAL and EE-SPFAL. Multiplicative
Inverse unit in S-box circuit [2] is taken as benchmark circuit to prove the efficiency of PFSAL. Table 1 depicts the FinFET parameters used in the realization of adiabatic logic circuits.
1. Comparison of Device Count
Table 4 depicts the device count of DPA resistant adiabatic logic circuits under consideration.
PFSAL utilizes 7 FinFETs for its buffer design. Likewise, 11 and 13 FinFETs are employed
in the design of XOR/XNOR and AND/NAND logic circuits. This is comparatively lower
than EE-SPFAL, CSSAL and SQAL logic circuit counterparts. FinSAL utilizes lower number
of transistors than PFSAL. It utilizes 6, 10, and 12 FinFETs in the design of BUFFER,
XOR/XNOR and AND/NAND logic circuits, which is less than PFSAL. It also depicts the
total number of logic gates utilized in design of multiplicative unit and total number
of FinFETs utilized in design of multiplicative unit. PFSAL utilizes 533 FinFETs,
which is less than the devices employed in CSSAL and EE-SPFAL. SQAL and FinSAL employs
439 and 533 number of FinFETs, which is less when compared with PFSAL.
Table 4. Effect of variation in number of Fins.
|
Adiabatic Logic
|
Logic Functions
|
No. of devices per logic gate
|
No. of logic gates in multiplicative unit
|
No. of devices in multiplicative unit
|
|
PFSAL
|
BUFFER
|
7
|
35
|
533
|
|
XOR/XNOR
|
11
|
12
|
|
AND/NAND
|
13
|
12
|
|
FinSAL
|
BUFFER
|
6
|
35
|
474
|
|
XOR/XNOR
|
10
|
12
|
|
AND/NAND
|
12
|
12
|
|
EE-SPFAL
|
BUFFER
|
8
|
35
|
592
|
|
XOR/XNOR
|
12
|
12
|
|
AND/NAND
|
14
|
12
|
|
CSSAL
|
BUFFER
|
11
|
35
|
889
|
|
XOR/XNOR
|
21
|
12
|
|
AND/NAND
|
21
|
12
|
|
SQAL
|
BUFFER
|
5
|
35
|
439
|
|
XOR/XNOR
|
9
|
12
|
|
AND/NAND
|
13
|
12
|
2. Secure Inverter/buffer Circuits
Fig. 8 illustrates the 3-dimensional graph depicting the energy dissipation of adiabatic
logic circuits while varying the frequency from 100 MHz to 1 GHz and also while varying
the supply voltage from 0.55 V to 0.9 V. It is obvious that CSSAL and SQAL consume
more energy than FinSAL, EE-SPFAL and PFSAL, respectively. EE-SPFAL consume very less
energy at lower frequencies and as frequency increases, the energy consumed by EE-SPFAL
increases exponentially since the leakage current becomes more dominant. In other
words, PFSAL consume less energy when compared with all other counterparts. Fig. 9 picturises the energy curve of CSSAL, EE-SPFAL, FinSAL, SQAL and PFSAL operating
at 125MHz frequency and a supply voltage of 0.9 V. PFSAL, FinSAL and EE-SPFAL consume
almost equal amounts of energy. EE-SPFAL consumes the lowest energy value among all
the secure adiabatic logic circuits. However, the leakage energy of EE-SPFAL is very
dominant. Table 5 depicts the leakage energy component comparison for all circuits. CSSAL and EE-SPFAL
circuits consume 3.03~fJ and 1.61~fJ energy values, respectively while operating at
125 MHz frequency. FinSAL and PFSAL consume 0.253 aJ and 0.811aJ, respectively. SQAL
consume the least leakage energy of all the circuits counterparts compared, which
is about 0.014 aJ.
Fig. 8. Energy vs frequency vs supply voltage for PFSAL, CSSAL, SQAL, FinSAL, and
EE-SPFAL.
Fig. 9. Energy transients of CSSAL, EE-SPFAL, FinSAL, SQAL, and PFSAL.
Table 5. Leakage energy of secure adiabatic logic circuits.
|
Adiabatic Logic Circuits
|
Leakage Energy
|
|
CSSAL
|
3.03E-15
|
|
SQAL
|
1.49E-20
|
|
FinSAL
|
8.11E-19
|
|
EE-SPFAL
|
1.61E-15
|
|
PFSAL
|
2.53E-19
|
The optimum frequency range of adiabatic logic circuit operation has been analysed
by varying the frequency from 50 Hz to 1 GHz. This is depicted in Fig. 10. Fig. 10 shows that the circuits are capable of operating down to a frequency value of 1KHz.
PFSAL consume minimum of 0.35 fJ energy at an optimum frequency of 10 KHz. However,
CSSAL consume an energy of about 4.27fJ at 10 MHz and SQAL consume an energy of 1.19fJ
at 1MHz frequency. FinSAL and EE-SPFAL consume minimum energy values of 0.42 fJ and
0.19 fJ, respectively at 1 KHz.
Fig. 10. Energy vs frequency.
Fig. 11 indicates the output transients of secure adiabatic logic circuits. The initial slope
is due to the switch ON time of the pFinFET device in the pull - up network in SQAL
and CSSAL circuits. PFSAL, FinSAL and EE-SPFAL circuits have a complete charging path
as the charging process continues through two parallel paths in the pull-up network.
Floating output nodes are also dominant in the CSSAL and SQAL circuits. These are
eliminated in PFSAL, FinSAL and EE-SPFAL, respectively due to the efficiency of the
circuit design.
Fig. 11. Output transients of secure adiabatic logic circuits.
Table 6 depicts the complete analysis of E$_{\min}$, E$_{\max}$, E$_{\rm avg}$, Standard
Deviation, NED% and NSD% of AND/ NAND various DPA resistant adiabatic logic circuits
such as SQAL, CSSAL, EE-SPFAL, FinSAL and PFSAL across the range of frequency values.
Normalized Energy Deviation of PFSAL is 0.017, 0.017, and 0.015 for 1.25 MHz, 12.5
MHz, and 125 MHz, which is very less when compared with all other circuit counterparts,
respectively. Normalised standard deviation of PFSAL is 0.008, 0.008, and 0.007 for
1.25 MHz, 12.5 MHz, and 125 MHz, respectively which is lower than all other counterparts.
This demonstrates the DPA resistant property of PFSAL. EE-SPFAL has lower E$_{\min}$,
E$_{\max}$ and E$_{\rm avg}$ when compared with all other existing counterparts. However,
NED and NSD is higher for all various input combinations.
Table 7 represents the XOR/ XNOR logic circuit analysis of E$_{\min}$, E$_{\max}$, E$_{\rm
avg}$, Standard Deviation, NED% and NSD% of AND/ NAND various DPA resistant adiabatic
logic circuits such as SQAL, CSSAL, EE-SPFAL, FinSAL and PFSAL across a range of frequency.
Normalized Energy Deviation of PFSAL is 0.009, 0.006, and 0.006 for 1.25 MHz, 12.5
MHz, and 125 MHz, respectively, which is very less when compared with all other circuit
counterparts.
Table 6. Analysis of AND/NAND logic gate designed using various DPA resistant adiabatic
logic circuits.
|
|
SQAL
|
CSSAL
|
EE-SPFAL
|
FinSAL
|
PFSAL
|
|
Freq(MHz)
|
1.25
|
12.5
|
125
|
1.25
|
12.5
|
125
|
1.25
|
12.5
|
125
|
1.25
|
12.5
|
125
|
1.25
|
12.5
|
125
|
|
E$_{min}$ (fJ)
|
0.186
|
0.186
|
0.174
|
0.222
|
0.225
|
0.232
|
0.014
|
0.013
|
0.014
|
0.190
|
0.192
|
0.195
|
0.169
|
0.171
|
0.179
|
|
E$_{max}$ (fJ)
|
0.253
|
0.230
|
0.214
|
0.230
|
0.233
|
0.239
|
0.016
|
0.016
|
0.016
|
0.198
|
0.200
|
0.204
|
0.172
|
0.174
|
0.182
|
|
E$_{avg}$ (fJ)
|
0.204
|
0.219
|
0.236
|
0.225
|
0.228
|
0.235
|
0.015
|
0.015
|
0.015
|
0.194
|
0.196
|
0.200
|
0.171
|
0.173
|
0.181
|
|
SD(fJ)
|
0.020
|
0.022
|
0.033
|
0.003
|
0.003
|
0.003
|
0.004
|
0.004
|
0.004
|
0.004
|
0.004
|
0.004
|
0.001
|
0.001
|
0.001
|
|
NED%
|
0.266
|
0.190
|
0.187
|
0.035
|
0.032
|
0.031
|
0.171
|
0.173
|
0.165
|
0.041
|
0.042
|
0.042
|
0.017
|
0.017
|
0.015
|
|
NSD%
|
0.098
|
0.099
|
0.141
|
0.016
|
0.014
|
0.013
|
0.088
|
0.088
|
0.084
|
0.020
|
0.020
|
0.020
|
0.008
|
0.008
|
0.007
|
Table 7. Analysis of XOR/XNOR logic gate designed using various DPA resistant adiabatic
logic circuits.
|
|
SQAL
|
CSSAL
|
EE-SPFAL
|
FinSAL
|
PFSAL
|
|
Freq (MHz)
|
1.25
|
12.5
|
125
|
1.25
|
12.5
|
125
|
1.25
|
12.5
|
125
|
1.25
|
12.5
|
125
|
1.25
|
12.5
|
125
|
|
E$_{min}$ (fJ)
|
0.180
|
0.182
|
0.184
|
0.216
|
0.219
|
0.222
|
0.013
|
0.013
|
0.013
|
0.194
|
0.190
|
0.188
|
0.166
|
0.168
|
0.169
|
|
E$_{max}$ (fJ)
|
0.223
|
0.227
|
0.250
|
0.226
|
0.228
|
0.229
|
0.015
|
0.014
|
0.014
|
0.198
|
0.193
|
0.190
|
0.167
|
0.169
|
0.170
|
|
E$_{avg}$ (fJ)
|
0.208
|
0.217
|
0.235
|
0.222
|
0.225
|
0.225
|
0.014
|
0.014
|
0.014
|
0.195
|
0.191
|
0.189
|
0.173
|
0.170
|
0.169
|
|
SD(fJ)
|
0.019
|
0.023
|
0.034
|
0.005
|
0.004
|
0.003
|
0.001
|
0.001
|
0.001
|
0.004
|
0.001
|
0.001
|
0.007
|
0.002
|
0.0005
|
|
NED%
|
0.193
|
0.196
|
0.265
|
0.045
|
0.039
|
0.030
|
0.081
|
0.077
|
0.075
|
0.021
|
0.016
|
0.012
|
0.009
|
0.006
|
0.006
|
|
NSD%
|
0.091
|
0.107
|
0.144
|
0.020
|
0.020
|
0.013
|
0.043
|
0.042
|
0.039
|
0.020
|
0.007
|
0.005
|
0.043
|
0.009
|
0.003
|
3. 4-Bit Multiplicative Unit of S-box Circuit
The multiplicative unit of 4-bit S-Box circuit design is operated at 1.25 MHz, 12.5
MHz, and 125 MHz frequency with a peak voltage of 0.9 V and an output nodal capacitance
of 1 fF. Fig. 12 depicts the energy consumption of SQAL, CSSAL, EE-SPFAL, FinSAL, and PFSAL for 1.25MHz,
12.5MHz, and 125MHz. At 12.5 MHz frequency, PFSAL consume 38.4 fF, whereas SQAL, CSSAL,
EE-SPFAL and FinSAL consume 54.3 fF, 57.4 fF, 26.1 fF, and 30.5 fF, respectively.
From figure, it is evident that PFSAL consume very less energy when compared with
its counterparts.
Fig. 12. Energy dissipation vs Frequency comparison of multiplicative unit.
V. CONCLUSION
In this article, the efficiency of FinFET based positive feedback symmetric adiabatic
logic is validated through the design of multiplicative unit of an S-box. Due to its
energy-efficient operation and unconventional CMOS structure, the PFSAL logic circuit
is highly appropriate for designing secure S-Box architectures. The circuits have
been designed to operate efficiently for lower frequency values, normally found in
security architectures. This property of PFSAL makes it appropriate to be utilized
in applications such as RFID tags, smart cards etc. In addition to this, PFSAL produce
uniform current and power traces irrespective of any input combinations which is the
primary reason behind the robustness against the side channel attacks. The simulated
results depict that the proposed PFSAL based circuit is 57%, 59% and 12% more energy
efficient than FinFET based SQAL, CSSAL, and FinSAL counterparts. NED% of SQAL, CSSAL,
FinSAL, and PFSAL are 0.193, 0.045, 0.021, and 0.009, respectively at 1.25 MHz. The
NED and NSD of PFSAL is lower than its other circuit counterparts. Hence, PFSAL can
be a power analysis robust logic which can be employed where low power consumption
and enhanced security are the quintessential properties expected.
References
X. Zhang and K. K. Parhi, ``High-speed VLSI architectures for the AES algorithm,''
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 9,
pp. 957–967, 2004.
A. Prathiba and V. S. K. Bhaaskaran, ``Lightweight S-box architecture for secure internet
of things,'' Information, vol. 9, no. 1, 13, 2018.
A. Prathiba and V. S. K. Bhaaskaran, ``Hardware footprints of S-box in lightweight
symmetric block ciphers for IoT and CPS information security systems,'' Integration,
vol. 69, pp. 266–278, 2019.
V. S. K. Bhaaskaran and J. P. Raina, ``Pre-resolve and sense adiabatic logic for 100
Khz To 500 Mhz frequency classes,'' Journal of Circuits, Systems and Computers, vol.
21, no. 5, 1250045, 2012.
V. S. K. Bhaaskaran and J. P. Raina, ``Differential cascode adiabatic logic structure
for low power,'' Journal of Low Power Electronics, vol. 4, no. 2, pp. 178-190, 2008.
V. S. Kanchana Bhaaskaran, "Dynamic pre-resolve charge recovery logic," Indian Patent
883/CHE/2011A, 2011.
V. S. K. Bhaaskaran and B. P. Bhuvana, ``Energy efficient pass transistor adiabatic
logic,'' 2017.
V. S. K. Bhaaskaran, ``Energy recovery performance of quasi-adiabatic circuits using
lower technology nodes,'' Proc. of India International Conference on Power Electronics
2010 (IICPE2010), 2011.
V. S. K. Bhaaskaran and J. P. Raina, ``Two-phase sinusoidal power-clocked quasi-adiabatic
logic circuits,'' Journal of Circuits, Systems and Computers, vol. 19, no. 2, pp.
335–347, 2010.
S. Kim, C. H. Ziesler, S. Member, M. C. Papaefthymiou, and S. Member, ``A True single-phase
energy-recovery multiplier,'' IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 11, no. 2, pp. 194–207, 2003.
A. J. Banu and A. Prathiba, ``Non-profiled partial nibble recovery on power attack
resilient adiabatic PRESENT block cipher through AI vulnerability assessment,'' IEEE
Access, vol. 13, pp. 85543-85562, 2025.
P. Teichmann, J. Fischer, F. R. Chouard, and D. Schmitt-Landsiedel, ``Design of ultra-low-power
arithmetic structures in adiabatic logic,'' Proc. of International Symposium on Integrated
Circuits, pp. 365–368, 2007.
P. Teichmann, Adiabatic Logic Future Trend and System Level Perspective, Springer
Series in Advanced Microelectronics, 2012.
C. Monteiro, Y. Takahashi, and T. Sekine, ``Charge-sharing symmetric adiabatic logic
in countermeasure against power analysis attacks at cell level,'' Microelectronics
Journal, vol. 44, no. 6, pp. 496–503, 2013.
S. D. Kumar, H. Thapliyal, and A. Mohammad, ``EE-SPFAL: A novel energy-efficient secure
positive feedback adiabatic logic for DPA resistant RFID and smart card,'' IEEE Transactions
on Emerging Topics in Computing, vol. 7, no. 2, pp. 281-293, 2019.
M. Khatir and A. Moradi, ``Secure Adiabatic Logic: a Low-Energy DPA-Resistant Logic
Style.,'' Cryptology ePrint Archive, Report 2008/123, 2008.
S. D. Kumar, H. Thapliyal, and A. Mohammad, ``FinSAL: FinFET based secure adiabatic
logic for energy-efficient and DPA resistant IoT devices,'' IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 37, no. 1, pp. 110–122, 2018.
B. D. Choi, K. E. Kim, K. S. Chung, and D. K. Kim, ``Symmetric adiabatic logic circuits
against differential power analysis,'' ETRI Journal, vol. 32, no. 1, pp. 166–168,
2010.
S. D. Kumar, H. Thapliyal, A. Mohammad, and K. S. Perumalla, ``Design exploration
of a symmetric pass gate adiabatic logic for energy-efficient and secure hardware,''
Integration, vol. 58, pp. 369–377, 2017.
H. S. Raghav, V. A. Bartlett, and I. Kale, ``Investigating the effectiveness of without
charge-sharing quasi-adiabatic logic for energy efficient and secure cryptographic
implementations,'' Microelectronics Journal, vol. 76, pp. 8–21, 2018.
A. J. Banu, A. Prathiba, and V. S. K. Bhaskaran, ``Optimized implementation of PRESENT
8-bit S-box structure in secure adiabatic logic,'' Proc. of IEEE International Conference
on Trends in Electronics and Informatics (ICOEI), 2022.
B. P. Bhuvana and V. S. K. Bhaaskaran, ``Positive feedback symmetric adiabatic logic
against differential power attack,'' Proc. of 31st International Conference on VLSI
Design and 17th International Conference on Embedded Systems (VLSID), pp. 149–154,
2018.
N. Paydavosi, S. Venugopalan, Y. S. Chauhan, J. P. Duarte, S. Jandhyala, and A. M.
Niknejad, ``BSIM-SPICE models enable FinFET and UTB IC designs,'' IEEE Access, vol.
1, pp. 201–215, 2013.
M. S. Badran, H. H. Issa, S. M. Eisa, and H. F. Ragai, ``Low leakage current symmetrical
dual-k 7 nm trigate bulk underlap FinFET for ultra low power applications,'' IEEE
Access, vol. 7, pp. 17256–17262, 2019.
D. Bhattacharya and N. K. Jha, ``FinFETs: From devices to architectures,'' in igitally-Assisted
Analog and Analog-Assisted Digital IC Design, Cambridge University Press, pp. 21–55,
2015.
J. P. Colinge and A. Chandrakasan, FinFETs and Other Multi-gate Transistors, Springer
Science & Business Media, 2008
Bhuvana B P is an Assistant Professor in Sathyabama Institute of Science and Technology,
Chennai. She obtained her under graduation degree in electronics and communication
engineering from Annamalai University (India), Tamil Nadu and her M.Tech. degree in
VLSI design from Sona College of Technology, Salem and she received a Ph.D. degree
from VIT Chennai. Her research areas include low power VLSI circuit design, adiabatic
logic design.
Prathiba A received her bachelor's degree in electronics and communication in 2002.
She obtained a master's degree in communication systems in 2006 and obtaind a Ph.D.
degree in 2020. She is working as an Associate Professor in VIT Chennai. Her research
areas are hardware design of cryptographic architectures, vulnerability modeling of
side channel attacks and lightweight cryptography.
Kanchana Bhaaskaran V S is a Professor in the School of Electronics Engineering
and Vice Chancellor at VIT University, Chennai and Vellore. She obtained her bachelor's
degree in electronics and communication engineering from Institution of Engineers
(India), Calcutta, an M.S. degree in systems and information from Birla Institute
of Technology and Sciences (BITS) Pilani and a Ph.D. degree from VIT University. With
more than 38 years of industry, research and teaching experience, Professor Bhaaskaran
served the Department of Employment and Training, Government of Tamil Nadu, IIT Madras,
Salem Cooperative Sugar Mills' Polytechnic College, SSN College of Engineering and
VIT University Chennai. Her areas of specialization include Low Power VLSI Circuit
Design, Microprocessor Architectures and Linear Integrated Circuits. She has published
around 110 papers in international and national journals and conferences, 4 books
on Linear Integrated Circuits and related topics for McGraw-Hill Education (India)
Private Limited, has two patents published and one filed. She is a reviewer for peer
reviewed international journals and conferences. Professor Bhaaskaran is the Fellow
of the Institution of Engineers (India), Fellow of the Institution of Electronics
and Telecommunication Engineers (India), Senior Member of the Institute of Electrical
and Electronics Engineers Inc., USA and Life Member of the Indian Society for Technical
Education.