I. INTRODUCTION

Body temperature is the most important biomarker for monitoring disease and health status of animals. In the case of electroceuticals, since they are devices already inserted into the body to measure nerve signals and stimulate nerves, core body temperature can also be measured simultaneously. If body temperature measurement is added to the electroceutical, it can be used for monitoring inflammatory responses at the nerve electrode site, monitoring local organ body temperature, pre-monitoring of patient health abnormalities, and monitoring biorhythms (ovulation, circadian rhythm). After the electroceutical is inserted into the human body, symptoms of infection may appear immediately after implantation, months, or years later ^[1-4]. Local organ body temperature monitoring can also be used for measuring brain temperature for treating traumatic brain injury, measuring kidney temperature for early detection of kidney transplant rejection, and monitoring frictional heat of artificial prostheses ^[5-9].

Specifications for medical thermometers can be found in ASTM's guide (ASTM E1112-10). The measurement range of the body temperature sensor should be a minimum of 35.5$^\circ$C or lower and a maximum of 41$^\circ$C or higher. The measurement accuracy of the body temperature sensor must be within a maximum error of $\pm$0.1$^\circ$C. It does not require a wide measurement range, high resolution, or fast measurement speed. It is inserted into the body and is battery-operated, so it requires ultra-low power.

Fig. 1 shows a schematic diagram of when a body temperature measurement sensing function is added to a traditional electroceuticals for nerve signal measurement and nerve stimulation. It is preferred that a temperature transducer for measuring body temperature be implemented together with the production of the neural electrode. Temperature transducers can be built into IC chips using BJTs or polysilicon resistors ^[10-13], thin film metals ^[14-18], or thermistors ^[19]. On-chip types such as BJT and polysilicon temperature transducers have low sensitivity and are difficult to place in a designated location away from the main device. The easiest way to install a temperature transducer on a neural electrode is to use the metal used in the neural electrode as a resistance temperature detector (RTD). It uses Au, Pt, Ni, or Cu as a method that utilizes the change in resistance of a thin metal pattern according to temperature change ^[14-18]. The RTD method has the disadvantage of having a low basic resistance value of usually several hundred Ohm and low temperature sensitivity, which requires a lot of current to flow. Thermistors have the advantage of being highly sensitive to temperature, but their nonlinearity is a disadvantage. However, in body temperature measurement applications, linearity can be secured because the measurement range is narrow, about 10 degrees. Also, the resistance is typically around 100 k$\Omega$, making it suitable as a temperature transducer in this paper.

Temperature sensors using a resistive transducer usually consist of a Wheatstone bridge section to convert the resistance change according to temperature into a voltage change, and a readout IC to read the voltage change of the Wheatstone bridge. The Wheatstone bridge method is widely used to measure transducers whose resistance changes due to changes in physical quantities such as temperature and pressure ^{[11,12,20,21]}. For low power consumption, the resistance value of the always-on thermistor must be large, and a power gating technique can be used to ensure that the sensor consumes power only when sensing temperature. Power gating has been effectively used in PPG driving to reduce power consumption ^[22,23]. Power gating methods can also be applied to sensors to reduce power consumption. S. Pan designed a temperature sensor for biomedical applications using a Wheatstone bridge consisting of a temperature converter and a delta-sigma modulator ^[12]. The Wheatstone bridge and readout integrated circuit (ROIC) consumed 6.6 $\mu$W of power in static operation, and the author insisted that the power consumption could be reduced to 700 nW when operated with power gating techniques.

In this paper, a power-saving method for a body temperature sensor is proposed. To reduce the power consumption of the Wheatstone bridge, we propose a dynamic Wheatstone bridge configuration. The dynamic Wheatstone bridge supplies current only when sampling information from the temperature transducer, and creates two virtual bridges for a short time with one bridge to produce differential output. In addition, the ROIC part uses a VCO and TDC instead of the conventional amplifier and ADC architecture, and the operating voltage is designed to be 0.6 V.

Section II describes the design of the proposed body temperature sensor circuit, Section III presents the post-layout simulation results, and Section IV summarizes the conclusions.

Fig. 1. Electroceuticals including body temperature sensing function.

II. CIRCUIT DESIGN

Fig. 2 shows the proposed body temperature sensor architecture. When the externally mounted thermistor (R${}_{\rm th}$) changes resistance according to body temperature change, it is converted into a proportional digital value in the CH_T circuit. It is configured as a digital element to facilitate low power consumption by lowering the operating voltage and to facilitate design conversion in various manufacturing processes. Specifically, the functional elements such as analog amplifiers, buffers, and ADCs that are commonly used in the past were not used. Except for the BRG block, all blocks that make up the temperature measurement channel (CH_T) are designed to use a 0.6 V operation voltage for low power. To eliminate the common mode effect, the SMP and VCO blocks after the BRG block have differential signal paths and generate differential results at the TDC.

A Wheatstone bridge can typically be used as a measurement configuration for a thermistor whose resistance changes depending on temperature. A Wheatstone bridge is simply composed of two parallel-connected voltage dividers consisting of two resistors. Voltage divider 1 consists of a transducer resistor at the top and a fixed resistor at the bottom, whereas voltage divider 2 consists of a fixed resistor at the top and a transducer resistor at the bottom. This configuration forms a differential signal path, making it robust to common mode disturbances. However, in terms of reducing power consumption, since the two voltage dividers in the Wheatstone bridge always consume current, so a method to reduce power consumption is needed. In this paper, we use a technique to dynamically form a Wheatstone bridge using a single voltage divider to reduce the average current consumption. It is a method of forming a dynamic Wheatstone bridge by obtaining the voltage value $V_{mp}$ from a voltage divider for a short time, and then obtaining the voltage value $V_{mn}$ from an inverted voltage divider for a short time.

Fig. 3 shows the detailed circuit diagram of the thermistor, BRG, and SMP blocks, and explains the operating principle based on the operating clock and main signals. In Phase_P ($t_{1} < t < t_{2}$, $t_{5} < t < t_{6}$), the voltage $V_{m}$ from the block BRG is sampled & held by the SMP${}_{P}$ block, and in Phase_N ($t_{3} < t < t_{4}$, $t_{7} < t < t_{8}$), the voltage $V_{m}$ from the block BRG is sampled & held by the SMP${}_{\rm N}$ block. When the blocks SMP${}_{\rm P}$ and SMP${}_{\rm N}$ hold after sampling, both of the blocks (SMP${}_{\rm P}$ and SMP${}_{\rm N}$) shift the sampled value down by $V_{LS}$ (0.6 V) and hold it.

Fig. 2. Proposed body temperature sensor architecture.

Fig. 3. Working principle (a) detail circuit diagram, (b) operation clock and main signals, (c) dynamic Wheatstone bridge.

Normal body temperature can vary depending on the animal, for example, it is 36.5$^\circ$C for humans, 38.5$^\circ$C for cows, and 41$^\circ$C for chickens. The body temperature measurement circuit (CH_T) can set the output of TDC to zero based on the normal body temperature of the applied animal, which improves linearity. If the body temperature is higher than the normal body temperature, the TDC value outputs a positive value, and if the body temperature is lower than the normal body temperature, the TDC value outputs a negative value. In order for the output of TDC to be zero, the output voltage $V_{m}$ of the BRG circuit should be equal to ${VDDH}/2$. For this reason, the resistor R${}_{\rm trim}$ should be adjustable to match the thermistor resistance value R${}_{\rm th0}$ at the normal body temperature. The trim resistor (R${}_{\rm trim}$) is designed to be adjusted in 16 points from a minimum of 38.3 k$\Omega$ to a maximum of 76 k$\Omega$ with 2.5 k$\Omega$ unit step. In other words, the normal body temperature setting can be adjusted from 29 to 44$^\circ$C with 1$^\circ$C step.

The resistor R${}_{\rm trim}$ of the BRG circuit forms a voltage divider together with the external thermistor (R${}_{\rm th}$). The switch SW${}_{\rm BRG1}$ connects the node IO_TH1 to VDDH (1.8 V) when the control signal $f_{p}$ is HIGH, connects the node IO_TH1 to 0 V when the control signal $f_{n}$ is HIGH, and the switch SW${}_{\rm BRG1}$ is in the disconnected state when both $f_{p}$ and $f_{n}$ are LOW. The switch SW${}_{\rm BRG2}$ connects the node $V_{bottom}$ to 0 V when the control signal $f_{p}$ is HIGH, connects the node $V_{bottom}$ to VDDH (1.8 V) when the control signal $f_{n}$ is HIGH, and the switch SW${}_{\rm BRG2}$ is in the disconnect state when both $f_{p}$ and $f_{n}$ are LOW.

The SMP block consists of capacitors that store the input signal and switches that control the operation. In the sample phase (Phase_P, Phase_N), the switches (SW${}_{\rm SMPp1}$, SW${}_{\rm SMPp2}$, SW${}_{\rm SMPn1}$, SW${}_{\rm SMPn2}$) are connected to transfer the input signal to the storage capacitor (C${}_{\rm SMPp1}$, C${}_{\rm SMPp2}$, C${}_{\rm SMPn1}$, C${}_{\rm SMPn2}$). The level shift switches (SW${}_{\rm SMPp3}$, SW${}_{\rm SMPp4}$, SW${}_{\rm SMPn3}$, SW${}_{\rm SMPn4}$) connect the below nodes ($V_{CSMPp1}$, $V_{CSMPp2}$, $V_{CSMPn1}$, $V_{CSMPn2}$) of the storage capacitors during the sample phase, and when it moves to the hold phase, the level shift switches connect the below node of the storage capacitors to 0 V thereby shifting the SMP output down by the voltage amplitude $V_{LS}$. The reason for the down level-shift is that the common mode signal ($V_{CMH}$) of the BRG has 0.9 V, which is half of VDDH (1.8 V), and the common mode signal ($V_{CML}$) of the subsequent stage of the SMP block has 0.3 V, which is half of VDDL (0.6 V), so the output common mode signal of the SMP block needs to be downshifted by 0.6 V ($V_{LS}$) from 0.9 V ($V_{CMH}$) to 0.3 V ($V_{CML}$). A basic sample-and- hold block consists of one switch and one storage capacitor, but in the SMP block, the basic sample and hold configuration is two-stage. The reason for using a two-stage configuration is to reduce the leakage of the charge stored in the storage capacitor. When the switch is turned off, leakage occurs in the switch due to non-ideality, and the larger the voltage difference formed across the switch, the more severe the leakage, so the change in the charge stored in the storage capacitor becomes more severe. To minimize this leakage, the voltage level of the turned-off switch must be kept the same. In the sampling phase, both the voltages ($V_{basep}$, $V_{basen}$) at the top of the first-stage storage capacitor (C${}_{\rm SMPp1}$, C${}_{\rm SMPn1}$) and the voltages ($V_{CP}$, $V_{CN}$) at the top of the second-stage storage capacitor (C${}_{\rm SMPp2}$, C${}_{\rm SMPn2}$) are sampled at the $V_{m}$ value of the BRG. Therefore, in the hold phase, the voltage across the OFF switches (SW${}_{\rm SMPp2}$, SW${}_{\rm SMPn2}$) of the second stage is the same value, so charge leakage of the second stage storage capacitor (C${}_{\rm SMPp2}$, C${}_{\rm SMPn2}$) does not occur.

In Phase_P, the switch control signal $f_{p}$ becomes HIGH, and in Phase_N, the switch control signal $f_{n}$ becomes HIGH. The switch control signals $f_{p}$ and $f_{n}$ are non-overlapping clocks that never become HIGH at the same time.

When the switch control signal $f_{p}$ becomes HIGH at time $t_{1}$, the Phase_P section begins. The external thermistor (R${}_{\rm th}$) and the BRG block are configured as shown in the left box of Fig. 3(b), and the node IO_TH1 is connected to VDDH (1.8 V) and the node $V_{bottom}$ is connected to 0 V. At this time, the output $V_{m}$ of the BRG block becomes $V_{mp}$ as shown in Eq. (1). In the SMP${}_{P}$ block, while the switch control signal $f_{p}$ is HIGH, the switches SW${}_{\rm SMPp1}$ and SW${}_{\rm SMPp2}$ are turned on, and SW${}_{\rm SMPp3}$ and SW${}_{\rm SMPp4}$ are connected to $V_{LS}$. The signal $V_{CP}$ of the SMP${}_{P}$ block outputs the signal $V_{mp}$ of the BRG.

At time $t_{2}$, the switch control signal $f_{p}$ becomes LOW and the sampled value from the SMP${}_{P}$ block is held. When the switch control signal $f_{p}$ is LOW, SW${}_{\rm SMPp1}$ and SW${}_{\rm SMPp2}$ are disconnected and SW${}_{\rm SMPp3}$ and SW${}_{\rm SMPp4}$ are connected to 0 V. The output $V_{CP}$ of SMP${}_{P}$ is a value lowered from $V_{mp}$ by $V_{LS}$, as shown in Eq. (2).

To prevent the HIGH of $f_{p}$ and $f_{n}$ from overlapping, $f_{p}$ becomes LOW at time $t_{2}$ and $f_{n}$ becomes HIGH at $t_{3}$. When the switch control signal $f_{n}$ becomes HIGH at time $t_{3}$, the Phase_N section begins. The external thermistor (R${}_{\rm th}$) and the BRG block are configured as shown in the right box of Fig. 3(b), and the node IO_TH1 is connected to 0 V and the node $V_{bottom}$ is connected to VDDH (1.8 V). At this time, the output $V_{m}$ of the BRG block becomes $V_{m}$${}_{n}$ as shown in Eq. (3). In the SMP${}_{\rm N}$ block, while the switch control signal $f_{n}$ is HIGH, the switches SW${}_{\rm SMPn1}$ and SW${}_{\rm SMPn2}$ are turned on, and SW${}_{\rm SMPn3}$ and SW${}_{\rm SMPn4}$ are connected to $V_{LS}$. The signal $V_{CN}$ of the SMP${}_{\rm N}$ block outputs the signal $V_{mn}$ of the BRG.

At time $t_{4}$, the switch control signal $f_{n}$ becomes LOW and the sampled value from the SMP${}_{\rm N}$ block is held. When the switch control signal $f_{n}$ is LOW, SW${}_{\rm SMPn1}$ and SW${}_{\rm SMPn2}$ are disconnected and SW${}_{\rm SMPn3}$ and SW${}_{\rm SMPn4}$ are connected to 0 V. The output $V_{CN}$ of SMP${}_{\rm N}$ is a value lowered from $V_{mn}$ by $V_{LS}$, as shown in Eq. (4).

If the thermistor (R${}_{\rm th}$) has a value of R$_{0}$ at normal body temperature ($T_{0}$) and has an NTC (Negative Temperature Coefficient of Resistance) characteristic where the resistance decreases as the temperature increases, the resistance of the thermistor can be expressed as in Eq. (5). Since the trimming resistance (R${}_{\rm trim}$) of the BRG block matches the thermistor resistance value $R_{0}$ at normal body temperature ($T_{0}$), the trimming resistor R${}_{\rm trim}$ has the resistance value $R_{0}$. In addition, since the level shift voltage ($V_{LS}$) is 1/3 of the voltage VDDH, the signals $V_{CP}$ and $V_{CN}$ can be simplified as in Eqs. (6) and (7), respectively.

Fig. 4 shows the circuit diagram and output characteristics of the voltage-controlled oscillator (VCO) block. The VCO changes the frequency of the generated clock (CLKx) proportionally according to the supplied voltage level (VCx). The VCO has an odd number of serially connected unit inverters (RING_UNIT), and the unit inverter consists of a serial connection of an inverter PMOS (M1), a current-regulating NMOS (M2), and an inverter NMOS (M3). The characteristics of the curve in the upper plot of Fig. 4(b) can be explained as follows. When the body temperature rises and the resistance value of the thermistor decreases, the resistance change ($\Delta R(T)$) from the resistance ($R_{0}$) at the normal body temperature increases. This causes an increase in the output $V_{CP}$ of the SMP${}_{\rm P}$, and accordingly, the frequency of the output clock $CLK_{P}$ of VCO${}_{\rm P}$ also increases. As a result, as the body temperature increases, the frequency of the output $CLK_{P}$ of the VCO${}_{\rm P}$ increases, as shown in the blue solid curve. On the other hand, the output $V_{CN}$ of SMP${}_{\rm N}$ decreases and therefore the frequency of the output clock $CLK_{N}$ of VCO${}_{\rm N}$ decreases. As a result, as the body temperature increases, the frequency of the output $CLK_{N}$ of VCO${}_{\rm N}$ decreases, as shown in the red dotted curve.

Fig. 4. Voltage controlled oscillator, (a) detail circuit diagram, (b) output characteristics according to body temperature.

A single VCO${}_{\rm X}$ has a short linear range of the output clock frequency for the input voltage $VC_{x}$, and the nonlinearity of the output clock frequency increases for high input voltage $V_{Cx}$. However, if two VCOs are used in a differential manner, the linearity is improved as shown in the lower curve of Fig. 4(b), and it can be sufficiently utilized for narrow-range applications such as body temperature measurement. For low power consumption, it is designed to operate at 0.6 V using a high threshold MOS.

Fig. 5 shows the structure of the time-to-digital converter (TDC) and the main clocks. The TDC receives clock $CLK_{P}$ from VCO${}_{P}$ and clock $CLK_{N}$ from VCO${}_{N}$ and outputs the difference between the two clock signal frequencies. The TDC block consists of two counters (CNT), a subtractor (SBTR), and a delay (DL). The counter CNT counts the number of rising edges of the input clock ($CLK_{P}$, $CLK_{N}$) in the time interval from the rising edge ($t_{11}$) of clock $f_{begin}$ to the rising edge ($t_{12}$) of clock $f_{end}$. The subtractor (SBTR) outputs the difference between DOUTP[:] corresponding to $CLK_{P}$ and DOUTN[:] corresponding to $CLK_{N}$ as DOUT[:]. The DONE signal is output so that the TDC conversion can be notified externally that it has completed. The output signal (DOUT[:]) of TDC should be used after the rising edge of the DONE signal occurs. The DONE signal slightly delays the $f_{end}$ signal as it passes through the DL. The TDC circuit is composed entirely of high threshold MOS for low power consumption and is designed to operate at 0.6 V.

Fig. 5. Time-to-digital converter (TDC), (a) circuit diagram, (b) clock diagram.

To reduce the power consumption of the Wheatstone bridge, current should be supplied only for a short period of time when sampling information for the VCO${}_{X}$ input, and no current should be consumed during the remaining measurement time. For example, the time taken for measurement, the time from $f_{begin}$ rising edge to $f_{end}$ rising edge, can be 1 second, and the HIGH duration of switch control signals ($f_{p}$ or $f_{n}$), which supplies current to the dynamic Wheatstone bridge, can be 1 ms. In this case, the average current flowing through the dynamic Wheatstone bridge can be reduced to about 0.2% of the peak current. The HIGH duration of the switch control signal ($f_{p}$, $f_{n}$) and the onset time of the rising edge of $f_{end}$ after the onset of the rising edge of $f_{begin}$ can be controlled by register setting.

III. SIMULATION RESULTS

Fig. 6 shows the layout of the body temperature measurement circuit CH_T. The total layout area including CH_T is $610$ $\mu$m $\times$ $180$ $\mu$m.

Fig. 6. Layout of the body temperature measurement circuit CH_T.

In order to verify the sensitivity and nonlinearity of the TDC output value to temperature change, a post-layout simulation was performed.

Fig. 7 shows an example of simulation waveforms of the main signals. The top waveform shows the waveform of the IO_TH2 port (i.e., $V_{m}$) of the BRG block. The middle waveform shows the output $V_{CP}$ of the SMP${}_{P}$ block and the output $V_{CN}$ of the SMP${}_{\rm N}$ block. The bottom waveform shows the output $CLK_{P}$ of the VCO${}_{\rm P}$ and the output $CLK_{N}$ of the VCO${}_{\rm N}$. A high voltage is sampled during sampling to SMP${}_{\rm P}$ around one second, and accordingly, VCO${}_{\rm P}$ outputs high frequency $CLK_{P}$, which appears as a solid block at that moment. While the high voltage value is sampled to SMP${}_{\rm N}$ for a moment, $CLK_{N}$ also outputs high frequency, which appears as a solid block at that moment.

Fig. 8 shows the TDC output according to temperature. The temperature range is 34$^\circ$C to 42$^\circ$C, which is the thermometer range specified in the ISO 80601-2-56 standard, and the TDC output was plotted at 1$^\circ$C intervals. Since R${}_{\rm trim}$ was set assuming 37$^\circ$C as the normal body temperature, we can see that the TDC output is close to 0 at 37$^\circ$C. As a result of the first linear regression, the coefficient of determination (R${}^{2}$) is 0.9998, and the slope, the temperature measurement sensitivity, is 2224 digits/$^\circ$C. Based on a temperature measurement sensitivity of 2224 digits/$^\circ$C, the temperature difference corresponding to 1 digit is 0.00045$^\circ$C.

Fig. 7. Simulation waveform of main signals.

Fig. 8. TDC output according to temperature change.

Fig. 9 shows the linear regression error over the thermometer measurement range. The blue triangle marks the linear regression error, and the brown dotted lines mark the acceptable error bounds. The accepted error boundary refers to the ASTM E1112-00 guide. Over the entire range from 34$^\circ$C to 42$^\circ$C, the negative error is as low as -0.05$^\circ$C, while the positive error is as high as 0.08$^\circ$C. According to ASTM E1112-00 guide, the temperature error should be less than $\pm$0.1$^\circ$C between 37$^\circ$C and 39$^\circ$C, the most precise temperature range. For the range from 37$^\circ$C to 39$^\circ$C, where the error should be the smallest, the negative error is as low as $-0.05^\circ$C, while the positive error is as high as $+0.03^\circ$C.

Fig. 9. Nonlinear errors and acceptable error boundary.

Fig. 10. Monte Carlo simulation results to check mismatch effects.

The total power consumption of the body temperature measurement circuit from the dynamic Wheatstone bridge to TDC is 112 nW at 37$^\circ$C. Fig. 10 shows the power consumption of the components of the temperature sensor. The two VCOs and the TDC, operating at 0.6 V, consume 14.5 nW, which accounts for about 13 % of the total power consumption. The dynamic Wheatstone bridge and SMP block consume 97.1 nW, which is 87 % of the total power consumption. While the traditional Wheatstone bridge technique consumed 28.1 $\mu$W of power, the dynamic Wheatstone bridge technique allowed the overall power consumption to be reduced to 112 nW.

Fig. 10 shows 900 data as the result of 100 Monte Carlo (MC) simulations. To reduce simulation time, only two VCOs are used in MC simulations. At each temperature, input the ideal voltage value corresponding to the voltage value of SMP${}_{\rm X}$ into VCO${}_{\rm X}$. After performing simulations for 9 cases in the temperature range of 34$^\circ$C to 42$^\circ$C in each MC simulation case, the linear regression was performed and the error was plotted. Out of the 100 MC simulations performed, only two cases exceeded the error boundary of 0.3$^\circ$C at 34$^\circ$C.

Fig. 11 shows the pnoise analysis results of the VCO. It has a corner point at about 2 kHz and shows 1/f noise characteristics at low frequencies. It has a value of -98.8 dBc/Hz at the relative frequency point of 1 kHz. The accumulated jitter up to 1 kHz is 2166 ppm, which corresponds to 6.5 Hz for the nominal frequency of 3 kHz. Considering the sensitivity of 0.00045 degrees/digit, this is equivalent to 0.003 degrees.

Fig. 11. Noise simulation results.

Fig. 12. Power consumption breakdown of body temperature sensor.

Table 1 shows a comparison of the body temperature sensor performance between previous works and this work. S. Minto et al. designed a body temperature measurement circuit using a typical static Wheatstone bridge and Delta Sigma ADC structure, and the power consumption reached 35 $\mu$W. S. Pan et al. designed a temperature sensor for biomedical applications using a conventional static Wheatstone bridge and a delta-sigma ADC architecture. To reduce power consumption, the Wheatstone bridge was composed of high-resistance resistors, and a power consumption of 6.6 $\mu$W was obtained. From an architectural perspective, there was no approach to reduce power consumption by using a dynamic Wheatstone bridge and a TDC that can be driven at low operating voltage.

In order to compare performance, an appropriate FoM is defined and compared accordingly, and one of them is the resolution${}^{2}$ FoM ^[24]. Resolution generally refers to the resolution of the ADC or TDC, or a value equivalent to the noise level. Usually, even if the noise level is small, the inaccuracy can have a larger value. Therefore, it is inefficient for the resolution to be too good compared to the inaccuracy, and in reality, it is sufficient if the sensor can express slightly more detailed information than the inaccuracy. That is, if the inaccuracy is 0.1$^\circ$C, 0.05$^\circ$C resolution is sufficient, but 0.0001$^\circ$C resolution is excessive. Therefore, when defining FoM, we should use the level of inaccuracy instead of resolution. In this case, it is appropriate to use the ratio of inaccuracy to the measurement range rather than the absolute value for inaccuracy information. Makinwa introduced FoM that multiplies the energy per conversion by the square of the relative inaccuracy in his 2010 paper ^[24]. However, since it is more reasonable to use the unsquared relative inaccuracy than the square of the relative inaccuracy, we introduced FoM that multiplies the energy per conversion by the relative inaccuracy. Since the energy required per unit conversion is multiplied by the relative inaccuracy, the smaller the value, the better the performance. As a result, the inaccuracy FoM value in this paper is 179 nJ/conv%, which is lower than 1100, 504, and 396 nJ/conv% in other previous studies.

One of the various performance metrics of a sensor is supply sensitivity, which indicates how much the output is affected by the supply power. The sensor used in this paper showed a supply sensitivity of 42$^\circ$C/V, which means that a 3.1 mV change in the supply voltage can cause an error of 0.13$^\circ$C, which is inaccuracy. An LDO can supply and regulate the supply voltage to a temperature sensor within a few mV fluctuations, but the supply sensitivity of this sensor needs to be improved.

V. CONCLUSION

An ultra-low-power body temperature readout circuit for implantable electroceuticals has been developed. In the Wheatstone bridge stage, the dynamic Wheatstone bridge technique was proposed to save power consumption and make differential signals. One bridge consisting of a thermistor and a trimmable resistor is utilized, and the current is only passed for a short time, and the bridge is reversed to obtain a differential signal. The temperature information obtained from the dynamic Wheatstone bridge is held in the following sample and hold block (SMP). In the SMP block, a technique is implemented to reduce leakage during the hold phase and to downshift the common mode level from 0.9 V to 0.3 V at the start of the hold phase for the subsequent 0.6 V operating blocks. The layout of the proposed low-power circuit was carried, and the post-layout simulation results showed that the temperature sensitivity was 2224 digits/$^\circ$C and the nonlinearity error was -0.05/+0.08$^\circ$C in the measurement range from 34$^\circ$C to 42$^\circ$C, satisfying the ASTM E1112-00 specification. The power consumption of the dynamic Wheatstone bridge including the thermistor and all subsequent circuits up to the TDC was 112 nW, demonstrating ultra-low power performance sufficient for applications in electroceuticals.