The semiconductor industry continuously pursues performance enhancement and power efficiency optimization through advanced miniaturization processes [1,2]. As the integration density of integrated circuits increases, the design of interconnect structures has become a critical factor in determining the performance of semiconductor devices [3]. Metal interconnects play a key role in signal transmission within semiconductor devices, and their electrical characteristics significantly impact overall circuit performance and reliability [4]. However, despite the nanometer-scale precision of semiconductor manufacturing processes, various errors can still arise due to process limitations. In particular, minor misalignment may occur during bonding, lithography, and etching processes.
When misalignment occurs in interconnect structures, the contact area at the bonding interface decreases, leading to an increase in contact resistance [5,6]. A higher contact resistance impedes current flow, resulting in reduced signal transmission speed, increased power consumption, and accelerated device degradation. In circuits that handle high-frequency signals, changes in resistance can further degrade signal integrity, ultimately compromising system reliability [7]. Therefore, it is essential to analyze the im pact of misalignment in interconnect and bonding structures on electrical properties and to explore strategies for minimizing its effects.
This study investigates the influence of misalignment on contact resistance and current flow in metal interconnect structures and seeks design approaches to mitigate resistance degradation even in the presence of misalignment [8]. Given that semiconductor fabrication inherently involves process-induced misalignment, it is necessary to propose an optimized design that ensures stable signal transmission characteristics within a certain tolerance range.
Fig. 1 illustrates the reduction in contact cross-sectional area in the current path when misalignment occurs in a bonding structure. As the bonding interface shrinks, contact resistance increases, leading to higher power loss and reduced signal transmission speed. To address this issue, it is crucial to optimize interconnect structures and conduct a detailed analysis of current density variations under misalignment conditions to improve power efficiency.
This study aims to propose an optimal structure that minimizes resistance increase and maintains power efficiency while considering inevitable misalignment in semiconductor interconnect design and bonding processes [9]. By doing so, this research is expected to enhance semiconductor device reliability and provide valuable guidelines for next-generation semiconductor fabrication and design.

Fig. 1. Illustration of misalignment in a hybrid bonding structure.

Fig. 1.

Illustration of misalignment in a hybrid bonding structure.

 One of the key factors determining the performance of semiconductor devices is power transmission efficiency, which is significantly influenced by the electrical characteristics of interconnect and bonding structures [10]. During semiconductor manufacturing, misalignment inevitably occurs due to various factors in the bonding process, which can reduce the effective contact area and consequently increase contact resistance [11,12]. Therefore, this study aims to analyze how the electrical characteristics of bonding structures change under different misalignment conditions and to propose design strategies for minimizing signal transmission degradation.
To achieve this, we investigated the impact of misalignment on the electrical properties of bonding interfaces in semiconductor interconnect structures. Finite element method (FEM)-based simulations were conducted to analyze variations in current flow and resistance under different misalignment conditions [13].
Fig. 2 conceptually illustrates the bonding structures analyzed in this study. Fig. 2(a) represents an ideal condition where the upper and lower structures are perfectly aligned, ensuring uniform current distribution and minimal contact resistance. In contrast, Fig. 2(b) depicts a misaligned condition in which the upper structure is laterally displaced, reducing the effective contact area between the bonding surfaces and thereby limiting the available conduction path [14].
As the contact area decreases, the current density per unit area increases under the same applied current, potentially leading to a rise in contact resistance. Consequently, signal transmission uniformity is compromised, and electrical performance deteriorates. In particular, excessive misalignment can result in asymmetric current flow paths, causing localized high current density regions that may affect the long-term reliability of the device.
To quantitatively evaluate these effects, this study conducted simulations to assess the voltage-current characteristics under varying degrees of misalignment. The experimental setup applied 3V to one end of the lower structure and 0V to the opposite end of the upper structure, establishing a potential difference across the bonding interface. By treating the structure as a single resistive element, changes in current flow were measured to compare overall resistance characteristics.
Beyond merely analyzing current and resistance values, this study also aimed to observe detailed current density distributions within the bonding interface. This approach enables the assessment of current density imbalance along the signal transmission path, providing a more precise analysis of variations in electrical characteristics [15]. The presence of localized high current density regions within the bonding interface could result in increased power dissipation and reliability degradation, which are critical factors for maintaining the long-term performance of semiconductor devices.
Therefore, this study visually analyzes the evolution of current density distribution as misalignment increases, providing structural design guidelines for optimizing interconnect and bonding configurations. The experimental methodology focuses not only on resistance measurements but also on detailed current density analysis within the bonding interface, offering a comprehensive evaluation of the electrical impact of misalignment [16]. Through these findings, this research aims to propose structural improvements for enhancing power transmission efficiency and contribute to the optimization of semiconductor interconnect and bonding design.

Fig. 2. (a) The bonding structure without misalignment (b) with misalignment.

Fig. 2.

(a) The bonding structure without misalignment (b) with misalignment.

  Prior to conducting the simulations, the current flow was analyzed by applying the voltage bias method proposed in the experimental setup, assuming the structure as a single resistive element. A potential difference was established by applying 3V to the end of the lower structure and 0V to the end of the upper structure, which served as the basis for evaluating the current density distribution and resistance variation at the bonding interface. Based on these conditions, FEM-based simulations using the Ansys Simulation Tool were conducted to analyze the resistance variations and current density distribution under different misalignment conditions. Through these simulations, the current flow paths within the bonding structure were visualized, and the quantitative changes in resistance as misalignment increased were evaluated.
Figs. 3 and 4 present the simulation results of the current density distribution at the bonding interface. Figs. 3 and 4 show the topmost surface of the lower metal line. The red dashed box indicates the junction area with the upper metal line. Fig. 3 illustrates the thermal profile and current density distribution when the misalignment varies from 0 to 20 mm in a metal interconnect structure with a line width of 20 mm, while Fig. 4 shows the distribution for a structure with a 40 mm line width and misalignment ranging from 0 to 40 mm. As shown in Fig. 3, the regions with higher current density exhibit higher temperatures, indicating that the thermal profile closely follows the shape of the current density distribution. The red dashed rectangular regions in each figure indicate the bonding interface between the upper and lower structures.
The simulation results reveal that, regardless of the line width, the current density remains low at the central region of the bonding interface. Additionally, a higher current density was observed at the metal edges opposite to the direction of the applied voltage, whereas the edges perpendicular to the current flow exhibited relatively lower current density. As the misalignment increased, this nonuniformity in current density distribution gradually diminished. Notably, the central region of the bonding interface maintained consistently low current density regardless of the misalignment magnitude, whereas the perpendicular edge regions exhibited an increasing trend in current density as misalignment became more pronounced. This suggests that misalignment does not result in a uniform change in current density across the bonding interface but rather redistributes the current density, concentrating it in specific regions. Consequently, even when composed of identical materials, the resistance may vary across different regions. If the regions prone to high current density can be identified and structurally expanded, the overall resistance of the structure can be reduced, thereby improving signal transmission efficiency.
An increase in current density indicates a concentration of current flow in specific regions, implying that structural changes lead to current path redistribution. However, this may also induce localized current crowding effects, necessitating consideration of the resulting electrical property variations. Therefore, when evaluating the impact of misalignment on the electrical characteristics of the bonding interface, it is crucial to recognize that misalignment not only reduces the total contact area but also redistributes current flow, altering the electrical equilibrium of the bonding structure.
Figs. 5(a) and 5(b) present the current density variations across different regions as a function of increasing misalignment for metal structures with 20 mm and 40 mm line widths, respectively. In the simulations, misalignment was applied by shifting the upper structure to the right, with the x-axis of each graph representing the degree of misalignment. The three curves in each graph represent the current density variations at the Top, Middle, and Bottom regions, which specifically refer to three distinct positions—upper, central, and lower points, respectively—along the left edge of the lower metal structure. The Bottom region is closest to the applied voltage, the Top region is the farthest, and theMiddle region corresponds to the area where the most significant variations in current density were observed in Figs. 3 and 4.
Through simulations, the impact of misalignment in bonding structures on current density distribution and resistance was analyzed. In the absence of misalignment, current density was primarily concentrated in the top and bottom metal regions, indicating that current flowed efficiently through these areas. In contrast, the middle region exhibited relatively low current density, as it contributed less to the primary current path.
As misalignment increased, noticeable changes in current density distribution were observed. The top metal region exhibited a higher current density than the bottom region, suggesting that current flow was asymmetrically redistributed due to misalignment. Notably, the middle metal region, which initially had a low current density, experienced a sharp increase as misalignment grew. These findings indicate that as misalignment increases, the regions of concentrated current shift, leading to localized increases in current density. This suggests that misalign ment does not merely reduce the effective contact area but also alters the current flow pattern, concentrating current in specific regions and modifying the overall signal transmission characteristics.
Based on this analysis, structural design improvements should be explored to enhance electrical signal transmission efficiency despite misalignment. By designing structures that maximize the effective conduction path, it may be possible to improve power efficiency through simple structural modifications rather than complex material changes.
In conclusion, optimizing the structure to ensure that the edge of the bonding interface interacts more extensively with the applied electrical signal can enhance overall signal transmission efficiency. Such a design approach could contribute to the optimization of interconnect and bonding structures in semiconductor devices.

Fig. 3. In a 20-mm width structure, the cross-sectional view of the bonding interface. Thermal profile (Temperature) and Current density profile are same.

Fig. 3.

In a 20-mm width structure, the cross-sectional view of the bonding interface. Thermal profile (Temperature) and Current density profile are same.

Fig. 4. In a 40-μmm width structure, the cross-sectional view of the bonding interface.

Fig. 4.

In a 40-μmm width structure, the cross-sectional view of the bonding interface.

Fig. 5. Current density distribution in a bonding metal structure with misalignment (a) 20-μm line width, (b) 40-μm line width.

Fig. 5.

Current density distribution in a bonding metal structure with misalignment (a) 20-μm line width, (b) 40-μm line width.

 In this study, the impact of misalignment on the electrical characteristics of the bonding interface was analyzed through simulations. To further validate these findings, experimental fabrication was conducted, followed by structural and electrical characterization of the bonded chips. The objective of the experiment was to evaluate changes in the bonding interface and resistance due to misalignment and to compare the experimental results with the simulation data.
Fig. 6 presents the bonded chip after the bonding process. Fig. 6(a) shows the external appearance of the bonded chip, where the mask was designed with probe pads at the wiring terminals to facilitate resistance measurements. Fig. 6(b) provides a scanning acoustic tomography (SAT) image of the bonding interface, enabling a visual inspection of the bonded region. This analysis allows verification of whether the bonding was successfully formed and provides insights into structural variations caused by misalignment.
Fig. 7 illustrates the resistance measurement results obtained using a probe station with a two-probe method after the bonding process. In the graph, the X-axis represents the percentage of misalignment, while the Y-axis denotes the measured resistance values. The primary objective of this experiment was to analyze how the decrease in bonding area affects overall resistance and to compare the results with simulation data.
Resistance values were measured by applying voltage sweeping within a range of -0.5 V to 0.5 V, and Ohm’s Law was used to calculate resistance based on the voltagecurrent characteristics of each structure [17]. The experimental results, as depicted in Fig. 7, demonstrate that resistance increases significantly with increasing misalignment. Notably, a sharp rise in resistance was observed when misalignment exceeded approximately 62.5%, indicating a nonlinear increase in resistance beyond a critical threshold. Since resistance is inversely proportional to the contact area—meaning that as the area decreases, resistance increases—it can be expected that as the misalignment ratio increases, the rate of resistance increase will follow an inverse proportional trend. For example, when the misalignment reaches 50%, the contact area is reduced by half, which might suggest that the contact resistance should double. However, due to the non-uniform distribution of current density across the contact area and the fact that contact resistance accounts for only a portion of the total resistance, the actual increase in resistance is significantly less than twofold. Moreover, as shown in Fig. 7, misalignment up to 25% results in a resistance variation of less than 5%, which is not considered significant. Therefore, a misalignment tolerance of up to 25% can be reasonably accepted as a design specification without causing meaningful degradation in electrical performance.
These findings are consistent with the simulation results, where increased misalignment led to localized current density concentration and distortion of current flow, thereby increasing overall resistance. The experimental validation confirms that as misalignment becomes more severe, the resistance of the interconnect rises, and the current density distribution exhibits asymmetric behavior. This study quantitatively analyzes the electrical impact of bonding misalignment, providing fundamental insights for optimizing interconnect design and process conditions in future semiconductor applications.

Fig. 6. (a) Photograph of the bonded chip after the bonding process. (b) Scanning Acoustic Tomography (SAT) image of the same chip, showing the internal structure and bonding interface.

Fig. 6.

(a) Photograph of the bonded chip after the bonding process. (b) Scanning Acoustic Tomography (SAT) image of the same chip, showing the internal structure and bonding interface.

Fig. 7. Measured resistance variation with misalignment percentage in the bonded structure.

Fig. 7.

Measured resistance variation with misalignment percentage in the bonded structure.

  This study investigates the impact of bonding misalignment on current density distribution and resistance variation in semiconductor packaging. Using FEM simulations (Ansys) and experimental validation, it analyzes how misalignment affects the bonding interface and electrical characteristics. Simulations show that without misalignment, current density is concentrated at the edges due to crowding. As misalignment increases, current redistribution becomes asymmetric, leading to a sharp rise in resistance beyond 62.5% misalignment due to reduced contact area. Experimental results confirm this trend. Since eliminating misalignment entirely is impractical, this study proposes a structural design approach to optimize electrical performance. By maximizing contact along the signal injection direction, current density imbalance can be mitigated, improving signal transmission efficiency. These findings provide a foundation for future semiconductor packaging design, emphasizing current distribution control and electrical reliability.

  This work was supported by was supported by Seoul National University of Science and Technology. The interconnect samples were fabricated using Sputtering System (SRN-110), S-FAB at Seoul National University of Science and Technology. The EDA tool was supported by the IC Design Education Center(IDEC), Korea.