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  1. (Departement of Electronics Engineering, Korea National University of Transportation, Chungju 380-702, South Korea)
  2. (Flash Product and Technology, Samsung Electronics Company, Hwaseong, South Korea)
  3. (School of Advanced Fusion Studies, University of Seoul, Seoul 130-743, South Korea)



Compact model, resistive-switching random-access memory (ReRAM), switching layer, Verilog-A, SPICE simulation

I. INTRODUCTION

Resistive-Switching Random-Access Memory (ReRAM) is a next-generation non-volatile memory device with compatible with CMOS process, fast switching time and low program voltage with a Metal-Insulator-Metal (MIM) structure [1]. Bipolar ReRAM consists of two terminals and stores data by controlling between a low resistance state (LRS) and a high resistance state (HRS). These states are achieved by controlling the formation and recombination of conductive filaments (CF) through the continuous arrangement of oxygen ion vacancy by voltage application. Due to these advantages and the characteristic of outputting current by controlling resistance through CF formation, ReRAM is employed in arrays to represent weights in neuromorphic and AI computing fields.

In this paper, we developed a Verilog-A model that can be directly applied to array simulations. The model selected and employed a formula primarily focused on current conduction from the available current formulas for quick simulation [2,3,4]. To validate the model, we calibrated it using experimental data reported for two types of ReRAM devices. The first device utilized SiN${}_{\rm x}$ as the switching layer [5]. The SiN${}_{\rm x}$ layer exhibited pores with an average size of 30 nm, distributed within a range of 20 to 50 nm. These structural characteristics were reported to minimize randomness in CF formation, resulting in more consistent device operation. The second device utilized HfO${}_{\rm x}$ as the switching layer, along with an additional Ge-Sb-Te (GST) layer to enhance CF stability [6]. While the thin HfO${}_{\rm x}$ layer could potentially increase randomness during operation, the GST layer was shown to mitigate this by localizing CF formation.

II. VERILOG – A COMPACT MODEL FOR RERAM

The flow of current during the operation of ReRAM is ultimately determined by the formation of CF and the electron tunneling distance gap determined accordingly. In this model, the calculation of the gap used an existing formula that simplifies the formation of CF (1). Additionally, the conduction of current is expressed using the following four Eqs. (2)-(5): Schottky emission, Poole-Frenkel (P-F) emission, space-charge-limited conduction (SCLC), and trap-assisted tunneling (TAT), in that order. Furthermore, since the thickness of the device with the thinnest switching layer among the two modeled devices is 10 nm (with both the Ge-Te-Se layer and the HfO${}_{\rm x}$ layer measuring 10 nm), formulas related to direct tunneling and Fowler-Nordheim (FN) tunneling were not employed. In ReRAM, the dominant formula for current in the HRS and LRS varies depending on the type of switching layer. Each equation shows a current output value with a unique slope according to the input voltage according to the physical properties. Accordingly, when determining the output current value in the model, the measured value was divided into HRS and LRS parts, and the current formula with a similar slope to the measured current value was designated as the dominant equation.

(1)
$ \frac{dg}{dt}=-v_0\exp \left(-\frac{E_a}{kT}\right)\sinh \left(a_0\frac{qV\gamma }{LkT}\right) , $
(2)
$ I (SCH)=A_0\frac{4\pi qm^*{(kT)}^2}{h^3}{\exp}\!\!\left[\!-\!\frac{q\left({{\Phi}}_{{B}}\!-\!\sqrt{\frac{{qE}}{{4}\pi \varepsilon }}\right)}{kT}\right] , $
(3)
$ I (PF)=A_1q\mu N_cE{\exp}\left[-\frac{q\left({{\Phi}}_{{\mathrm T}}-\sqrt{\frac{{qE}}{{4}\pi \varepsilon }}\right)}{kT}\right] , $
(4)
$ I (SCLC)=A_2\frac{9}{8}{\varepsilon }_i\mu \theta \frac{V^2}{L^3} , $
(5)
$ I \left(TAT\right)=A_4{\exp} \left(-\frac{8\pi \sqrt{2qm^*}}{3hE}{\Phi}^{\frac{3}{2}}_{\mathrm{T}} \right) , $

where, $E_{a}$ is the activation energy for oxygen ions to generate or recombine the vacancy, L is switching layer thickness , $a_{0}$ is atomic hopping site distance, $E$ is electric field applied to the device, $\mu$ is electron mobility in the switching layer, $N_{c}$ is the density of states in the conduction band, $m^{*}$ is electron effective mass in the switching layer, $\Phi_{B}$ is junction barrier height, $\Phi_{T}$ is electron trap energy at the edge of the conduction band, $\theta$ is the ratio of free and shallow trapped charge, and $\gamma$, $v_{0}$, $A _{1}$, $A_{2}$, $A _{3}$, $A{4}$ are fitting parameters [2,3,7].

III. SELECTION OF MAJOR CURRENT EQUATION

As mentioned in the previous paragraph, when the physical properties of the current equation are input, all equations have a constant slope regardless of the fitting parameters.

Fig. 1 compares the measured output of 10 DC cycles for a SiN${}_{\rm x}$ based ReRAM device with calculated values derived from various current equations. Consistent with prior studies [8], the output current in ReRAM devices follows a dominant current equation. To identify the most appropriate equation, the SET/RESET process was divided into HRS and LRS regions, and the equation with the closest slope to the measured data was selected. This approach reduced computational complexity, making it efficient for large scale array simulations while maintaining accuracy. For HRS modeling, the P-F Emission equation provided the best fit, with TAT added to enhance accuracy in the SET-HRS region. The SET-LRS region was modeled using the P-F Emission equation, ensuring alignment with experimental results.

The model parameters were assigned on the basis of the fabrication characteristics, which are outlined in the following list: $\Phi_{\rm B} = 0.7$ eV, $\Phi_{\rm T} = 0.3$ eV, $\theta = 0.1$, insulator carrier mobility $= 0.1$ cm$^2$/Vs, SiN${}_{\rm x}$ relative permittivity $= 7$, and effective carrier mass ($m_{e}$) $= 0.5 m_{o}$ [9,10,11,12,13].

Fig. 2 illustrates the modeling of a ReRAM device that incorporates HfO${}_{\rm x}$ and Ge-Se-Te layers as the switching layer to ensure stable state conversion. Unlike the SiN${}_{\rm x}$ based device, which is modeled with a single current equation, the thin switching layer and the GST layer in this device necessitate the use of combined current equations for accurate modeling. In the HRS region, the Schottky Emission formula was applied for low-voltage conditions, while the P-F Emission formula was utilized for high-voltage conditions. In the LRS region, the current output was modeled by integrating the Schottky Emission and SCLC formulas, represented as the cyan curve in the figure. This approach demonstrates that devices with complex switching layers can be effectively modeled using a combination of multiple current equations.

The parameters used in the model include a HfO${}_{\rm x}$ insulator permittivity of 22, an insulator carrier mobility of $4 \times 10^{-12}$ cm$^2$/Vs, $m _{e} = 0.5 m_{o}$, and $\Phi_{B} = 0.7$ eV [14,15,16].

In the case of Fig. 3(a), the device utilizes SiN${}_{\rm x}$ as a switching layer, and the measured and modeled values can be calibrated using only a single current equation. Therefore, both HRS and LRS in SET can be modeled using the P-F Emission equation, and in RESET, HRS is modeled using the P-F Emission equation, and LRS is modeled using the equations of SCLC. Also, in the case of Fig. 3(b), HfO${}_{\rm x}$ and Ge-Se-Te layers were used as switching layers, so modeling could not be performed using only one current equation. Accordingly, modeling was carried out by outputting the sum of the two current equations. For the SET process, HRS was modeled using Schottky Emission and P-F Emission equations, and LRS was modeled using Schottky Emission and SCLC equations. During the RESET process, P-F Emission equation was used for HRS, Schottky emission and SCLC equations were used for LRS below $-1$ V, and only Schottky Emission equation was used for $-1$ V and above.

Fig. 1. Modeling of SET operation according to the current equation of a ReRAM device with SiN${}_{\rm x}$ as a switching layer.

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Fig. 2. Modeling of SET operation according to the current equation of a ReRAM device with HfO${}_{\rm x}$ and Ge-Se-Te as a switching layer [6].

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Fig. 3. (a) ReRAM device modeling using SiN$_{\rm x}$ layer as switching layer. (b) ReRAM device modeling using HfO$_{\rm x}$ and Ge-Se-Te as switching layers [7].

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IV. CONCLUSION

In this study, we developed a voltage-current density equation for ReRAM modeling, which can be automatically selected based on the gap width and implemented using Verilog-A for efficient large-scale SPICE simulations. It was found that once the material properties are determined, adjusting the fitting parameters does not change the slope of the output current graph, allowing for fast modeling. The primary current mechanism in ReRAM is governed by the material characteristics, and when a single equation is insufficient, the sum of two equations can accurately represent the current flow. Additionally, we demonstrated high consistency in modeling devices with SiN${}_{\rm x}$ and HfO${}_{\rm x}$ as switching layers. These results show that fast and reliable ReRAM modeling is achievable for devices with various materials as switching layers.

ACKNOWLEDGMENTS

This research was supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT of Korea (MSIT) (RS-2023-00258527), and in part by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT(2022M3I8A1077243).

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Gyunseok Ryu
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Gyunseok Ryu received his B.S. degree from the Department of Electronics Engineering, Korea National University of Transportation, Korea, in 2023. From 2023 to 2024, he is currently a master student at Korea National University of Transportation. His current research interests include operation conditions, reliability and cell characteristics of memory.

Jongwon Lee
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Jongwon Lee received his B.S. and M.S. degrees from the Department of Electronics Engineering, Korea National University of Transportation, Korea, in 2022, and 2023, respectively. In 2022, he joined at Samsung Electronics Company Ltd. His interests include 3D NAND flash memory and ReRAM.

Myounggon Kang
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Myounggon Kang received his Ph.D. degree from the Department of Electrical Engineering, Seoul National University, Seoul, Korea, in 2012. From 2005 to 2015, he worked as a senior engineer at Flash Design Team of Samsung Electronics Company Ltd. From 2015 to 2024, he joined Korea National University of Transportation as a professor of Department of Electronics Engineering. In 2024, he joined University of Seoul as a professor of School of Advanced Fusion Studies. His current research interests are CMOS device modeling and circuit design of memory.