Mobile QR Code QR CODE

The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

Journal Search

  1. Home
  2. Archive
  3. 2026-06 (Vol.26 No.03)
  4. 10.5573/JSTS.2026.26.3.228
XML PDF INFO REF

REFERENCES

1 
M. Manguoglu, A. H. Sameh, O. Schenk, 2011, A domain-decomposing parallel sparse linear system solver, Journal of Computational and Applied Mathematics, Vol. 236, No. 3, pp. 319-325DOI
2 
W. L. Hamilton, 2020, Graph Representation Learning, Morgan & ClaypoolGoogle Search
3 
L. Page, S. Brin, R. Motwani, T. Winograd, 1999, The PageRank citation ranking: Bringing order to the web, Stanford InfoLabGoogle Search
4 
S. Park, H. Kim, J. Kim, 2025, A fault-tolerant GEMM accelerator with online error detection and correction based on systolic array architecture, Journal of Semiconductor Technology and Science, Vol. 25, No. 3DOI
5 
S. Choi, K. J. Lee, Y. Kim, H.-J. Yoo, 2020, A 9.52 ms latency, and low-power streaming depth-estimation processor with shifter-based pipelined architecture for smart mobile devices, Journal of Semiconductor Technology and Science, Vol. 20, No. 3, pp. 255-266DOI
6 
B. Lu, X. Qiao, J. Bhatt, 2019, Redesk: A reconfigurable dataflow engine for sparse kernels on heterogeneous platforms, Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 1-8DOI
7 
J. Fowers, G. Brown, P. Cooke, G. Stitt, 2014, A high memory bandwidth FPGA accelerator for sparse matrix-vector multiplication, Proceedings of the IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines, pp. 36-43DOI
8 
A. K. Jain, H. Omidian, H. Fraisse, M. Benipal, L. Liu, D. Gaitonde, 2020, A domain-specific architecture for accelerating sparse matrix vector multiplication on FPGAs, Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, pp. 127-132DOI
9 
S. Li, D. Niu, K. T. Malladi, H. Zheng, B. Brennan, Y. Xie, 2021, Optimized data reuse via reordering for sparse matrix-vector multiplication on FPGAs, Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 1-9DOI
10 
C. Liu, H. Yin, C. Cheng, X. Li, 2023, Towards high-bandwidth-utilization SpMV on FPGAs via partial vector duplication, Proceedings of the 28th Asia and South Pacific Design Automation Conference, pp. 198-203Google Search
11 
T. A. Davis, Y. Hu, 2011, The University of Florida sparse matrix collection, ACM Transactions on Mathematical Software, Vol. 38, No. 1, pp. 1-25DOI
12 
H. Kim, E. Ham, S. Park, H. Kim, J. Kim, 2023, A DRAM bandwidth-scalable sparse matrix-vector multiplication accelerator with 89% bandwidth utilization efficiency for large sparse matrix, Proceedings of the IEEE Asian Solid-State Circuits Conference, pp. 1-3DOI