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The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

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  3. 2025-08 (Vol.25 No.04)
  4. 10.5573/JSTS.2025.25.4.355
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References

1 
J. Lee, H. Valavi, Y. Tang, and N. Verma, ``Fully row/column parallel in-memory computing SRAM macro employing capacitor based mixed-signal computation with 5-b inputs,'' Proc. of 2021 Symposium on VLSI Circuits, pp. 1-2, 2021DOI
2 
H. Jia and M. Ozatay, ``A programmable neural-network inference accelerator based on scalable in-memory computing,'' Proc. of 2021 IEEE International Solid- State Circuits Conference (ISSCC), pp. 236-237, 2021.DOI
3 
S. Kim, S. Kim, S. Um, S. Kim, K. Kim, and H. -J. Yoo, ``Neuro-CIM: A 310.4 TOPS/W neuromorphic computing-in-memory processor with low WL/BL activity and digital-analog mixed-mode Neuron firing,'' Proc. of 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), pp. 38-39, 2022.DOI
4 
Y. Wang, ``Energy efficient RRAM spiking neural network for real time classification,'' Proc. of the 25th edition on Great Lakes Symposium on VLSI, pp. 189-194, 2015.DOI
5 
K. Goetschalckx and M. Verhelst, ``DepFiN: A 12 nm, 3.8TOPs depth first CNN processor for high res. image processing,'' Proc. of 2021 Symposium on VLSI Circuits, pp. 1-2, 2021.DOI
6 
Z. Chen, X. Chen, and J. Gu, ``15.3 A 65 nm 3T dynamic analog RAM-based computing-in-memory macro and CNN accelerator with retention enhancement, adaptive analog sparsity and 44TOPS/W system energy efficiency,'' Proc. of 2021 IEEE International Solid- State Circuits Conference (ISSCC), pp. 240-242, 2021.DOI
7 
S. Xie, C. Ni, A. Sayal, P. Jain, F. Hamzaoglu, and J. P. Kulkarni, ``16.2 eDRAM-CIM: Compute-in-memory design with reconfigurable embedded-dynamic-memory array realizing adaptive data converters and charge-domain computing,'' Proc. of 2021 IEEE International Solid- State Circuits Conference (ISSCC), pp. 248-250, 2021.DOI
8 
S. Xie, C. Ni, P. Jain, F. Hamzaoglu, and J. P. Kulkarni, ``Gain-cell CIM: Leakage and bitline swing aware 2T1C gain-cell eDRAM compute in memory design with bitline precharge DACs and compact schmitt trigger ADCs,'' Proc. of 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), pp. 112-113, 2022.DOI
9 
T. Tanzawa and T. Tanaka, ``A dynamic analysis of the Dickson charge pump circuit,'' IEEE Journal of Solid-State Circuits, vol. 32, no. 8, pp. 1231-1240, Aug. 1997.DOI