Mobile QR Code QR CODE

The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

Journal Search

  1. Home
  2. Archive
  3. 2025-06 (Vol.25 No.03)
  4. 10.5573/JSTS.2025.25.3.257
XML PDF INFO REF

References

1 
Y. Dong G. Giles, G. L. Li, J. Rearick, J. Schulze, and J. Wingfield, ``Maximizing scan pin and bandwidth utilization with a scan routing fabric,'' Proc. of IEEE International Test Conference, pp. 1-10, 2017.DOI
2 
A. Sehgal, J. Fitzgerald, and J. Rearick, `` Test cost reduction for the AMDTM Athlon processor using test partitioning,'' Proc. of IEEE International Test Conference, pp. 1-10, 2007.DOI
3 
``IEEE Standard Testability Method for Embeded Core-based Integrated Circuits,'' IEEE Std 1500-2022 (Rivision of IEEE Std 1500-2005), pp. 1-168, 2022.DOI
4 
``IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device,'' IEEE Std 1687-2014, pp. 1–283, 2014.DOI
5 
E. J. Marinissen and Y. Zorian, ``IEEE Std 1500 enables modular SoC testing,'' IEEE Design & Test of Computers, vol. 26, no. 1, pp. 8-17, 2009.DOI
6 
K.-J. Lee, T.-Y. Hsieh, C.-Y. Chang, Y.-T. Hong, and W.-C. Huang, ``On-chip SOC test platform design based on IEEE 1500 standard,'' IEEE Transactions on Very Large Scale Integration Systems, vol. 18, no. 7, pp. 1134-1149, 2010.DOI
7 
Z. Zhong, G. Li, Q. Yang, and K. Chakrabarty, ``Access-time minimization for the IJTAG network using data broadcast and hardware parallelism,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 1, pp. 185-198, 2021.DOI
8 
F. G. Zadegan, Z. Zhang, K. Petersén, and E. Larsson, ``Reusing IEEE 1687-compatible instruments and sub-network over a system bus,'' Proc. of IEEE International Test Conference, pp. 219-228, 2022.DOI
9 
P. Bernardi, M. Rebaudengo, M. S. Reorda, and M. Violante, ``A P1500-compatible programmable BIST approach for the test of embedded flash memories,'' Proc. of Design, Automation and Test in Europe Conference and Exhibition, pp. 720-725, 2003.DOI
10 
``IEEE Standard for Test Access Port and Boundary-Scan Architecture,'' IEEE Std 1149.1-2013(Revision of IEEE Std 1149.1-2001), pp. 1-444, 2013.DOI
11 
V. Yellapragada, S. Raman, B. Shivaray, L. Romain, B. NadeauDostie, and M. Keim, ``Implementing design-for-test within a tile-based design methodology - Challenges and solutions,'' Proc. of IEEE International Test Conference in Asia, pp. 43-48, 2018DOI
12 
J. F. Côté, M Kassab, W. Janiszewski, R. Rodrigues, R. Meier, and B. Kaczmarek, ``Streaming scan network (SSN): An efficient packetized data Nnetwork for testing of complex SoCs,'' Proc. of IEEE International Test Conference, pp. 1-10, 2020DOI
13 
A. Q. Ansari, M. R. Ansari, and M. A. Khan, ``Performance evaluation of various parameters of network-on-chip (NoC) for different topologies,'' Proc. of Annual IEEE India Conference, pp. 1-4, 2015DOI
14 
A. Kamath, G. Saxena, and B. Talawar, ``Analysis of ring topology for NoC architecture,'' Proc. of International Conference on Computing and Network Communications, pp. 381-388, 2015DOI