1. Overall Architecture

Fig. 2(a) shows the overall architecture of the proposed KWS processor. It consists of two CIM clusters, and each cluster integrates eight CIM cores. The processor also includes a 16 KB input activation (IA) buffer, a weight buffer, a top controller, and a non-linear activation single instruction multiple data (SIMD) core, all communicating through an interconnect network. The SIMD core performs activation and batch normalization between convolution layers. The CIM core consists of a $144\times 144$ 3T2C eDRAM CIM array. Among the 144 rows, 16 rows are allocated to operate as the capacitive digital-to-analog converters (CAP-DACs) used in the SP-ADCs, while 16 columns are reserved for sign-bit computation ^{[21, 22]}, where the MACs are shifted positive and offset-canceled to restore the signed result. It also integrates a bitline (BL) and wordline (WL) driver, an ADC/core controller, DW/PW switch, and a digital adder for partial sum accumulation. Fig. 2(b) shows the schematic of the 3T2C eDRAM bitcell. The access transistor P1 employs an HVT-PMOS to minimize the leakage current while allowing the storage node (SN) to be charged up to VDD from the write bitline (WBL). In addition, the read bitline (RBL) is driven through charge coupling according to the read wordline (RWL) signal to generate the output voltage. Fig. 2(c) shows the operand table of the 3T2C bitcell. During computation, the RBL is pre-discharged to GND. Then, the RWL drives the RBL voltage rise through the activated N0 when SN stores 1, executing the analog AND operation.

Fig. 2. (a) Overall architecture of the proposed KWS processor, (b) schematic, and (c) operand table of the 3T2C eDRAM bitcell.

2. Frequency-selective Stride Feature Extraction

Fig. 3(a) depicts the operation of the FSSC. A one-second, one-dimensional raw audio signal consisting of 16,384 samples is fed into a sinc convolution layer. The signal is decomposed into amplitudes corresponding to different frequency bands for subsequent feature extraction in this layer. In the low-frequency domain, the signal varies slowly over time. Therefore, even with a large stride in convolution, the resulting accuracy degradation remains negligible. On this basis, the FSSC selectively applies different stride sizes to each frequency band to minimize the size of the input feature maps in the convolution layer. The stride sizes that minimize accuracy degradation were determined as hyperparameters, based on the kernels of the trained sinc convolution layer. The model is then fine-tuned with the selected strides to minimize the accuracy loss.

Fig. 3. (a) Frequency-selective stride convolution, (b) proposed kernel fusion architecture, and (c) performance comparison.

Although FSSC reduces IFM size, varying strides cause non-uniform IFM lengths that complicate parallel processing. To address this, a kernel fusion architecture based on structural re-parameterization is introduced, as shown in Fig. 3(b). During offline training, consecutive linear convolutions are mathematically collapsed into a single equivalent kernel. By applying this fused kernel directly to the raw input using the maximum stride, the network bypasses intermediate irregular feature maps. Consequently, it directly outputs uniform IFMs, which enables hardware-friendly parallel processing without additional computational overhead.

Fig. 3(c) illustrates the performance improvement achieved by the FSSC. As the stride size increases in the sinc convolution layer, both the input IFM size and the accuracy decrease, exhibiting a trade-off between computational efficiency and performance. Nevertheless, when the stride is increased up to 128, the accuracy drop remains as small as 0.8%, while the IFM size is reduced by 99.22%. As a result, the computational load of the subsequent DSCONV layers becomes significantly smaller, effectively addressing the challenges of raw audio processing.

3. Multi-stationary CIM Architecture

Fig. 4(a) depicts the throughput enhancement in the DWCONV layer enabled by the proposed multi-stationary CIM architecture. In conventional CIM architectures, DWCONV utilizes only a single memory column at a time, since each channel employs distinct weights. Fig. 4(b) introduces GDCONV to maximize DWCONV computation. The proposed architecture maximizes weight reuse and CIM utilization by training DWCONV to share identical weights across multiple channels. In particular, the frequency-domain features obtained via sinc convolution exhibit high similarity across adjacent channels, which enables weight sharing between consecutive channels while minimizing accuracy loss. To further improve CIM utilization with this model, the processor adopts IA stationary mapping in DWCONV. All IAs sharing identical kernels are mapped to a single CIM macro. The corresponding weight is broadcast via WL, allowing simultaneous computation across all columns.

Fig. 4. (a) Multi-stationary CIM architecture, (b) operation of the GDCONV computation, and (c) performance improvements in DWCONV layers.

Fig. 4(c) illustrates the performance improvement achieved by the multi-stationary CIM architecture. GDCONV achieves weight sharing across 16 channels without reducing the channel dimension, which constrains the accuracy loss to less than 2%. Furthermore, the IA-stationary architecture results in a $16\times$ improvement in DWCONV throughput. Consequently, GDCONV combined with the IA-stationary architecture leads to a $1.47\times$ improvement in the KWS system throughput.

4. Layer Fusion for Minimized Memory Footprint

Fig. 5 depicts the proposed layer fusion architecture, which is designed to minimize the memory footprint. In this work, the DSCONV network, following the sinc convolution, has an IFM size of 128 points $\times$ 128 channels $\times$ 8 bits in DWCONV, and a weight size of 128 input channels (IC) $\times$ 128 output channels (OC) $\times$ 8 bits in PWCONV. Therefore, each CIM cluster is designed to provide full on-chip storage for either the IFM or the weights, thereby eliminating the external memory accesses. The PWCONV outputs are directly committed into the CIM array of the next cluster through the same memory write path, without any column-level buffering or data reshaping stalls. As a result, the transfer overhead between PWCONV and DWCONV is substantially reduced. On the other hand, the DWCONV results are stored in the IA buffer, whereas the other CIM cluster simultaneously updates its weights, thereby enabling seamless pipelined execution. Finally, by applying layer fusion between the DWCONV and PWCONV layers, the memory footprint is reduced by 47.5% compared to the identical design without layer fusion.

Fig. 5. Proposed layer fusion CIM architecture.

5. Scalable-Precision ADC

Fig. 6(a) shows the hardware structure of the proposed SP-ADC. It consists of a CAP-DAC, a sense amplifier (SA), a 7-bit register, an ADC controller, and a voltage integrator. The SP-ADC incorporates distinct CAP-DACs dedicated to the conversion of the most significant bits (MSBs) and the least significant bits (LSBs), respectively. The MSB DAC is implemented with 48C (32C + 16C) to convert the two MSB bits, while the LSB DAC employs 16C capacitors to convert the remaining bits. The MSB DAC is charged by a voltage integrator circuit shared within the CIM core. The LSB DAC consists of sixteen dummy bitcells to minimize area overhead. It is also incorporated into the reference generation path, providing inherent noise calibration. The SP-ADC operates in a successive approximation register (SAR) architecture. It sequentially reconstructs the multibit multiply-and-accumulate (MAC) results from the analog voltage.

Fig. 6. (a) Hardware structure, (b) operational details, and (c) energy reduction of the SP-ADC.

Fig. 6(b) illustrates the operational sequence of the proposed SP-ADC. After the MAC operation in the first cycle, the sign bit is detected, and the subsequent three cycles are dedicated to converting the two MSBs. Instead of rail-to-rail switching of the large MSB capacitor, the SP-ADC employs an integrator-based ramping scheme. A shared voltage integrator generates a stepwise ramp voltage that accumulates charge equivalent to 48C over three steps, which is distributed to each column via local current mirrors. The current mirror is disabled once the target range is determined by the comparator, thereby halting further charging of the MSB DAC. In inlier cases with a limited output range, energy consumption is reduced by limiting the number of comparator evaluations and restricting switching activity to the small LSB capacitances. Even for outlier cases, conversion energy is reduced by early termination of the MSB ramp, leveraging the output distribution of neural networks ^[22]. After the MSB conversion phase, the SAR controller activates the LSB DAC to convert the remaining LSBs.

Fig. 6(c) shows the energy reduction of the SP-ADC. The integrator-based charging circuit reduces capacitor-driving energy, which otherwise increases with bit precision in conventional SAR ADCs. In particular, for outlier cases where the operation range exceeds $\pm 16$, the proposed SP-ADC reduces the average energy consumption of the CIM macro by 27.12% compared to the baseline ^[8]. For inlier cases within the $\pm 16$ range, the MSB-DAC switching energy is fully eliminated, resulting in a total energy reduction of up to 75.71%. In conclusion, the proposed SP-ADC effectively reduces the ADC conversion energy for KWS processing by exploiting the output data distribution inherent to KWS models.

1. Comparison with Conventional Structures

Fig. 7 shows the chip layout and hardware performance specification of the proposed processor. The processor is designed and verified via post-layout simulations in Cadence Virtuoso and Innovus with a 28 nm CMOS process. The 3T2C eDRAM achieves a retention time of 70.1 $\mu$s, utilizing a 0.61 fF metal–oxide–metal capacitor stacked across the M3–M7 layers with a 0.46 $\mu\text{m}^2$. It consumes 117.2 $\mu$W of maximum power consumption at 1.0 V operating voltage and 100 MHz frequency. It achieves 34.8 TOPS/W of macro energy efficiency and 21.6 TOPS/W of system energy efficiency. The processor achieves 95.1% accuracy on the 10 keywords of the Google Speech Commands dataset ^[23] with unknown and silence. It also achieves 98.4% accuracy on the Hey Snips ^[24] wake word detection task and 91.3% accuracy on the UrbanSound8K dataset ^[25]. As a result, the proposed processor can operate robustly across various acoustic signal processing tasks.

Fig. 7. Chip layout, performance specification, and benchmark results of the proposed processor.

Fig. 8. Simulation results of (a) MAC linearity under Monte Carlo simulation, (b) performance specification of the SP-ADC.

Fig. 8(a) illustrates the MAC linearity of the proposed CIM processor based on post-layout simulations. To evaluate the impact of process variations, including those in the 3T2C eDRAM bitcells, post-layout Monte Carlo simulations were conducted. The results show a 2-mV standard deviation in the MAC voltage, ensuring stable computation across 128 levels. Fig. 8(b) presents the integral nonlinearity (INL) and differential nonlinearity (DNL) of the SP-ADC. Extracted from post-layout simulations at a 100-MHz clock frequency, the maximum INL and DNL are 0.38 LSB and 0.26 LSB, respectively. Furthermore, the SP-ADC achieves a 41.6-dB SNR and a 6.62-bit ENOB. As a result, the proposed CIM processor ensures linear MAC operations and accurate data conversion across various practical operating conditions.

Fig. 9. Normalized performance improvements and evaluated accuracy.

Fig. 9 compares the proposed design to a baseline that consists only of the same CIM core count, without the proposed features. As the feature map size is significantly reduced by the FSSC, the energy consumption and latency are reduced by 88% each. Furthermore, according to the GDCONV and the SP-ADC, energy consumption and latency are reduced by 99% and 95%, respectively, compared to the baseline without any optimization. On the other hand, the processor shows a 2.3% accuracy loss due to the trade-off between accuracy and hardware performance. In conclusion, the proposed processor significantly reduces the energy consumption and latency of KWS processing while minimizing the accuracy loss.

Table 1 summarizes the performance comparison with prior KWS processors. The proposed design achieves 29.6% lower inference energy than the NPU-based KWS processor in ^[4] and demonstrates a $1.85\times$ improvement in energy efficiency compared to the CIM-based architecture in ^[6]. Furthermore, by leveraging a sinc convolution network ^[12] to support direct feature extraction from raw audio signals, it attains the highest accuracy on the Google Speech Commands dataset ^[23] among the referenced works. As a result, the proposed processor proves its effectiveness for ultra-low-energy KWS operations.