I. INTRODUCTION

Battery management systems (BMS) must sense each cell voltage with mV-level accuracy to detect over-voltage, under-voltage, and thermal events in EV packs. In many architectures, the ΔΣ analog-to-digital converter (ADC) performance is ultimately limited by the stability of its on-chip reference. When the reference exhibits temperature drift, the BMS compensation loop re-injects error into the measured cell voltage, which is undesirable for protection-grade systems. Accurate voltage references are indispensable in battery management systems, as they directly determine the accuracy of cell-voltage measurements, state-of-charge (SoC) estimation, and protection thresholds. Even a small deviation of a few millivolts can lead to substantial SoC errors or trigger premature over-voltage and under-voltage protection, compromising battery safety and lifetime. Therefore, the voltage reference in a BMS must maintain ultra-low temperature drift, typically within 5 ppm/°C, equivalent to less than 1 mV variation over a -20°C to 100°C temperature range ^{[1- 3]}.

In conventional battery management systems (BMS), each cell is measured through a direct electrical connection between the battery and the control unit. However, this approach poses a serious reliability concern under fault or fire conditions, since physical wiring can transmit thermal or electrical damage directly to the BMS, leading to system failure ^{[4- 6]}. To address this issue, a recent study proposed an indirect voltage-sensing technique that eliminates the physical connection between the BMS and the battery ^{[7, 8]}. In this method, a closed circuit was configured using the battery and an LED, and the cell voltage was inferred from the LED’s brightness. A reference LED (Ref. LED) was used to correct brightness variations caused by temperature, and the system achieved high accuracy (≤ 1 mV error) while operating the LED in the sub-threshold region.

Based on the reference voltage, a temperature compensation design is implemented to ensure that BMS monitoring results remain within 1 mV over the temperature range of -20°C to 100°C. The underlying premise of the reference voltage is that ideally, it shouldn’t change with temperature. However, in real operating environments, the reference voltage does vary with temperature, and this variation introduces additional error into the BMS monitoring results ^[8].

Therefore, it is essential to maintain a constant reference voltage across temperature variation, as this work aims to achieve BMS monitoring accuracy within 1 mV by specifying a 2.03 ppm/°C temperature coefficient requirement for the reference design.

To overcome these limitations, the proposed reference voltage employs a stacked PMOS-only array operating in the triode region to generate discrete voltage levels, combined with a two-stage digital trimming decoder that provides a reference voltage with a fine-step resolution of 1 mV. Temperature stability is obtained by composing a complementary to absolute temperature (CTAT) weak-triode and a proportional to absolute temperature (PTAT) deep-triode current components within the array and tuning their relative weights through gate-width optimization, yielding a composite temperature coefficient of 0.61 ppm/°C with reference voltage variation of 0.3 mV within the temperature range from (-20°C to 100°C). The temperature coefficient (TC, in ppm/°C) is defined as $TC = (\Delta V_{REF}/(V_{REF}\cdot \Delta T))\times 10^6$ (ppm/°C).

II. RELATED WORKS

Conventional BMS reference generators are predominantly bandgap-based, providing a temperature-compensated output around 1.2 V. Although such circuits achieve ppm-level stability, they require additional amplification to reach the 3-4 V range used in battery-monitoring ADCs, which increases area and temperature drift. MOS-only references have been reported to improve CMOS compatibility, including PMOS body-effect and subthreshold-driven structures, but these often exhibit higher temperature coefficients or limited trimming resolution. Therefore, a CMOS-only, high-side reference that combines CTAT/PTAT current shaping with body-bias tuning is required to meet mV-level BMS accuracy.

Fig. 1 shows a typical BMS cell voltage measurement path. Individual cells are multiplexed to the ΔΣ ADC through a cell-sensing buffer, a stable high-side. The lower part shows the X-cell battery pack, the cell-sensing/mux block, and the ΔΣ ADC/comparator. The reference voltage ($V_{REF}$) is supplied from an on-chip voltage reference and buffer. In this work, the block labeled ‘Conventional / Proposed Voltage Reference’ is replaced by the proposed PMOS-only, temperature-compensated reference voltage ^{[10, 11]}.

Fig. 1. BMS cell-voltage measurement architecture.

III. PROPOSED BMS REFERENCE VOLTAGE ARCHITECTURE

To overcome the limitations of the bandgap, as shown in Fig. 2, the proposed integration of a PMOS-only, temperature-compensated voltage reference into a typical BMS cell-voltage measurement chain. In parallel with the cell path, the ADC receives a precise on-chip reference voltage. In the conventional approach, this block is a bandgap or resistor-based reference; in this work, it is replaced by a PMOS-triode reference voltage with body-effect bias, as shown in the block on the left. The fine and coarse decoders select one of the stacked PMOS triode taps to realize a 3.2-4.2 V reference with 1 mV resolution, while the temperature compensation network combines CTAT current in weak-triode and PTAT current in deep-triode behaviors, and a body-effect biasing module regulates source-to-body voltage ($V_{SB}$) to suppress temperature drift to 0.3 mV across the temperature range of -20°C to 100°C. These are combined through an operational amplifier to deliver the final stable reference voltage with high precision, resolution steps of 1 mV, and a temperature coefficient of 0.61 ppm/°C, for a battery management system (BMS).

Fig. 2. Architecture of the programmable voltage reference ladder.

IV. CIRCUIT DESIGN OF THE PMOS-ONLY REFERENCE VOLTAGE

1. PMOS-based Reference Voltage

PMOS transistors were chosen over NMOS devices due to their superior qualities for precision reference applications within a 5 V CMOS environment. The PMOS structure allows operation close to the supply rail, providing ample voltage headroom for the stacked-array configuration. This headroom geometry is ideal for a stacked triode ladder that produces millivolt-scale drops per device. Since each element only requires a small $V_{SD}$ (<$ V_{SG} - |V_{TH}|$), the ladder remains firmly in the triode region, maintaining linearity, monotonicity, and fine resolution without needing boosted supplies. The high-side PMOS also integrates smoothly with per-device N-well isolation, enabling body-bias options for temperature trimming, whereas in similar NMOS isolation near the top rail is more complicated. PMOS devices are preferred because a 5 V SVT CMOS stacked to deliver a 3.2 V to 4.2 V reference voltage near the upper rail, with the PMOS transistor in the triode region, achieves millivolt resolution from 3.2 V to 4.2 V as a high-precision reference voltage for a battery management system. Additionally, the body of each PMOS device (n-well) can be independently biased, allowing precise control of the ($V_{SB}$) and threshold-voltage modulation needed for temperature compensation. PMOS devices also have lower subthreshold leakage compared to NMOS counterparts. Although PMOS devices occupy slightly more space, the overall circuit remains compact because it excludes BJTs and resistors, resulting in a total area of only 0.0038 mm². Fig. 3 illustrates the proposed CMOS reference ladder structure. The precision reference voltage using a high-side PMOS ladder (near VDD) was chosen over NMOS because it preserves gate headroom for 3.2-4.2 V outputs, enables millivolt-level triode drops, and allows per-device body-bias temperature trimming. Fig. 3(a) V_REF steps versus tap index showing high-side PMOS ladder close to VDD and low-side NMOS ladder from GND. Fig. 3(b) PMOS stacked ladder used for mV-level trimming near VDD. Fig. 3(c) NMOS stacked ladder used for low-side operation.

The operation of a PMOS transistor in the triode region to generate a voltage reference using a stacked array of PMOS transistors enables a finely quantized reference voltage with 1 mV resolution steps. In the triode region, each PMOS behaves as a resistor, characterized by an effective on-resistance $R_{ON}$.

Fig. 3. Architecture of the programmable voltage reference ladder.

Each PMOS device in the stacked ladder is biased in the triode region ($V_{SG} > |V_{TH}|$, $V_{SD} < V_{SG} - |V_{TH}|$), so it behaves as a voltage-controlled resistor from Eqs. (1) to (3)

(1)

$R_{ON} \approx \frac{1}{\mu_p C_{ox} \frac{W}{L}(V_{SG} - |V_{TH}|)},$

(2)

$R_{ON} \propto [\mu_p C_{ox}(W/L)(V_{SG} - |V_{TH}|)]^{-1},$

(3)

$V_{REF} \approx \sum_{i=1}^{N} V_{SD,i}.$

The reference level is the sum of the $N$ small drain-source drops, $V_{REF} \approx \sum_{i=1}^N V_{SD,i}$, and for a uniform ladder, the unit step is approximately $V_{REF}/N$, where $\mu_p$ is the hole mobility, $C_{ox}$ is the oxide capacitance per unit area, is the transistor aspect ratio, and $V_{TH}$ is the threshold voltage. When connected in series, the effective resistance of the stack is the sum of the unit resistances, distributing the applied bias nearly evenly across all transistors. Since the proposed stacked-triode PMOS ladder, each PMOS operates as a voltage-controlled resistor, so the total reference is the sum of the series drops. Therefore, $V_{REF}$ is directly governed by device sizing ($W/L$), bias overdrive ($V_{SG} - |V_{TH}|$), and their temperature dependence through $\mu_p(T)$ and $V_{TH}(T)$. This explains why adjusting gate width and body-bias ($V_{SB}$) in our design effectively tunes the ladder’s equivalent resistance, enabling temperature-slope compensation.

2. Gate Width Sizing for Temperature Compensation

The proposed reference voltage exploits two temperature-dependent current components generated by stacked PMOS devices biased at two distinct triode operating points (weak-triode and deep-triode). As shown in Fig. 4(a), PMOS devices biased in the weak-triode region produce a CTAT current that decreases with temperature. Fig. 4(b) A stacked PMOS $V_{SB}$ generator, biased by a common $V_{SG\_BIAS}$, operates in deep-triode and provides a bulk-bias (bulk tap) voltage, $V_{SB}$, to all ladder PMOS devices, enabling body-effect tuning of $|V_{TH}|$. Fig. 4(c) The deep-triode branch exhibits a PTAT current that increases with temperature. By sizing the PMOS devices, the CTAT and PTAT slopes are matched to achieve a nearly independent reference. For a PMOS transistor operating in triode, the drain-current magnitude can be approximated as

(4)

$|I_D| = \mu_p(T)C_{ox}\frac{W}{L}\left[(V_{SG} - |V_{TH}(T,V_{SB})|)V_{SD} - \frac{V_{SD}^2}{2}\right].$

Here, $\mu_p(T)$ is the hole mobility, and ($V_{SG}, V_{SD}, V_{SB}$) determine the operating point set by the surrounding stacked ladder network. The temperature dependence of $|I_D|$ arises from (i) mobility degradation $\mu_p(T)$, (ii) the threshold-voltage variation $|V_{TH}(T,V_{SB})|$ including body effect, and (iii) bias-point drift through $V_{SG}(T)$ and $V_{SD}(T)$. Differentiating Eq. (4) yields a first-order slope decomposition

(5)

$\frac{d|I_D|}{dT} \approx \underbrace{\frac{\partial |I_D|}{\partial \mu_p}\frac{d\mu_p}{dT}}_{\text{CTAT(mobility)}} + \underbrace{\frac{\partial |I_D|}{\partial |V_{TH}|}\frac{d|V_{TH}|}{dT}}_{\text{PTAT/CTAT(threshold,body)}} + \underbrace{\frac{\partial |I_D|}{\partial V_{SD}}\frac{dV_{SD}}{dT}}_{\text{bias-point drift}}.$

Since $d\mu_p/dT < 0$, the weak-triode branch (small $V_{SD}$) is designed such that the mobility term dominates, leading to negative current slope $dI_{CTAT}/dT < 0$.

(6)

$|V_{TH}(T,V_{SB})| = |V_{TH0}(T)| + \gamma\left(\sqrt{2\Phi_F + V_{SB}} - \sqrt{2\Phi_F}\right),$

where $\gamma$ is the body-effect coefficient and $\Phi_F$ is the Fermi potential. Therefore, the stacked $V_{SB}$ generator provides a controllable bulk-bias $V_{SB}$ that reshapes $d|V_{TH}|/dT$ and enables precise balancing between CTAT and PTAT components.

The weak-triode branch producing a CTAT current component, and a deep-triode branch producing a PTAT current component. Therefore, the total bias current is expressed as

(7a)

$I_{SUM}(T) = I_{CTAT}(T) + I_{PTAT}(T),$

and its first-order temperature coefficient is

(7b)

$\frac{dI_{SUM}}{dT} = \frac{dI_{CTAT}}{dT} + \frac{dI_{PTAT}}{dT},$

Temperature compensation is achieved when the opposite slopes satisfy

(7c)

$\frac{dI_{CTAT}}{dT} = -\frac{dI_{PTAT}}{dT} \Longrightarrow \frac{dI_{SUM}}{dT} \approx 0.$

The ladder is driven by a composite current that can be written as a weighted sum in Eq. (8)

(8)

$I_{TOTAL}(T) = \alpha I_{CTAT}(T) + \beta I_{PTAT}(T),$

where $\alpha$ and $\beta$ represent the effective scaling of each branch set by device segmentation (number of enabled unit devices) and gate sizing (effective $W/L$). Since the stacked triode ladder is monotonic in bias current, $V_{REF}(T)$.

(9a)

$\frac{dI_{TOTAL}}{dT} = \alpha\frac{dI_{CTAT}}{dT} + \beta\frac{dI_{PTAT}}{dT},$

And the cancellation condition

(9b)

$\alpha\left|\frac{dI_{CTAT}}{dT}\right| \approx \beta\left|\frac{dI_{PTAT}}{dT}\right|.$

So that $dV_{REF}/dT = 0$.

The role of gate width $W$ is the primary knob to tune the ratio $\alpha/\beta$ because each branch current scales approximately with ($W/L$) at its respective operating point. Increasing $W$ (for fixed $L$) increases the branch transconductance factor $\mu_p C_{ox}(W/L)$, but the net impact on $\alpha/\beta$ is different for the weak-triode and deep-triode branches because of their bias sensitivities $\partial I/\partial |V_{TH}|$ and $\partial I/\partial V_{SD}$ which shows in Eq. (5). Therefore, sweeping $W$ provides a practical way to match $|dI_{CTAT}/dT|$ and $|dI_{PTAT}/dT|$ around the mid-temperature point, while the $V_{SB}$ generator offers a continuous tuning knob to reduce residual curvature across the full range.

Fig. 7 shows that the PMOS triode array produces complementary temperature trends $I_{CTAT}$ decrease with temperature while $I_{PTAT}$ increases, so their sum can cancel temperature slope. It also demonstrates that gate width $W$ is the main tuning knob that sets the relative CTAT/PTAT weighting at $W = 40\ \mu\text{m}$, $I_{SUM}$ has a CTAT-dominant negative slope (about 105-95 $\mu$A), while at $W = 60\ \mu\text{m}$ it becomes PTAT-dominant with a positive slope (about 95-108 $\mu$A). The slope reverses sign with $W$ and is nearly zero at $W = 50\ \mu\text{m}$, where $I_{SUM} \approx 100\ \mu\text{A}$ from -20°C to 100°C, meeting the cancellation condition in Eq (9b). Thus, $W$ provides first-order temperature compensation to flatten $V_{REF}(T)$, and $V_{SB}$ is then used as a secondary knob to further suppress residual curvature.

Fig. 4. Temperature-compensated PMOS ladder using CTAT and PTAT branches.

3. Body Effect-based Compensation

Experimentally verifies that the proposed reference can use body effect as a continuous knob to shape the PMOS triode current over temperature. First, Fig. 5(a) shows the simulated PMOS threshold voltage $|V_{TH,P}|$ versus temperature for several source-bulk voltages $V_{SB}$. As $V_{SB}$ is increased from 0.1 V to 0.4 V, the entire curve shifts upward, i.e., $|V_{TH,P}|$ becomes larger at every temperature. This is the classic body-effect behavior, which confirms that the bulk terminal can be deliberately weakened to reduce the PMOS conduction. Next, Fig. 5(b) converts this threshold shift into current for a PMOS biased in triode with the same $V_{SG}$, the drain current $I_D$ decreases almost linearly as $V_{SB}$ increases. The linear fit in Fig. 5(b) closely follows the measured/simulated points, which indicates that the dependence is predictable and can be used in design.

Fig. 5. Body-effect-assisted temperature-compensated of the proposed PMOS ladder.

Fig. 5(c) further shows that this reduction in current holds across temperature for higher $V_{SB}$, not only is the current level lower, but the current-temperature slope is also reduced.

Finally, Fig. 5(d) presents the actual $V_{SB}$ generator used in the chip, which is a stacked PMOS network biased by a common $V_{SG\_BIAS}$ to keep all devices in deep triode. This block produces the required reverse body-bias voltage and drives the common N-well of the PMOS ladder. The proposed reference can be tuned by body-bias control.

V. MEAUREMENT RESULTS

This section evaluates the output programmability of the proposed PMOS array reference voltage. Using the coarse decoder, the reference voltage can be swept from 3.2 V up to 4.2 V in 32 mV increments, as shown in Fig. 6(a). This range covers the typical cell-monitoring window required in BMS applications. To enable accurate calibration of the ADC/comparator, a second fine decoder is activated around the lower end of the range; Fig. 6(b) demonstrates that a 4-bit fine code provides 1 mV resolution steps from 3.220 V to 3.250 V. The monotonic behavior of both curves confirms that the stacked-triode ladder and the digital decoding network are functioning as intended. As shown in Fig. 7, the weak-triode branch generates a CTAT current ($dI_{CTAT}/dT < 0$), while the deep-triode branch generates a PTAT current ($dI_{PTAT}/dT > 0$). By sweeping the PMOS gate width $W$, the relative CTAT/PTAT weighting is adjusted, and the sum current becomes nearly temperature-independent at $W = 50\ \mu\text{m}$, satisfying the cancellation condition in Eq. (9b).

Fig. 6. Programmable reference-voltage characteristic of the proposed PMOS ladder.

Fig. 7. CTAT (Weak Triode) and PTAT (Deep Triode) branch currents versus temperature for different PMOS gate widths, showing current cancellation. (a) W = 40 μm, (b) W = 50 μm, (c) W = 60 μm.

In Fig. 8, the measurements confirm that the PMOS triode array exhibits clean PTAT behavior, drain current increases nearly linearly with temperature, and that the body-effect bias $V_{SB}$ provides a precise knob to set both the DC level and the PTAT slope. With no body effect bias, the reference varies by about 1.5 mV across -20°C-100°C, but at the optimal $V_{SB}$ 0.2 V, the drift shrinks to 0.3 mV variation at 4.128 V over the range corresponding to an ultra-low temperature coefficient of 0.61 ppm/°C.

Fig. 8. VREF versus temperature for different body-bias voltages.

In Fig. 9, the chip microphotograph and evaluation board of the proposed temperature-compensated PMOS-only voltage reference. The 180-nm CMOS core, including the coarse/fine digital trim decoders, PMOS-based reference generator, $V_{SB}$ generator, and output OPAMP, occupies an active area of approximately 0.0038 mm². The bottom photo shows the evaluation PCB with coarse/fine trim control and the on-board power-supply block.

Fig. 9. Chip micrograph and evaluation board of the proposed system. VSB denotes the source-to-body voltage.

Table 1 shows that the proposed 180-nm PMOS-triode CTAT/PTAT reference achieves the lowest TC (0.61 ppm/°C) and the smallest $\Delta V_{REF}$ (0.3 mV) over -20 to 100°C with a compact area of 0.0038 mm². The FoM in Table 1 further confirms its superior efficiency by jointly reflecting temperature span, TC, power, and area. In the target BMS IC, the reference is powered by an internal LDO-regulated supply rail, so supply ripple and line variations are suppressed at the system level.

FoM is defined as $\text{FoM} = \frac{(\Delta T)^2}{TC\cdot P\cdot A}$, where $\Delta T$ is the temperature span (°C), TC is the temperature coefficient in ppm/°C (used numerically in ppm/°C), $P$ is the power consumption in W, and $A$ is the active area in mm². A higher FoM indicates better overall efficiency (low TC achieved with low power and small area over a wide temperature range). FoM values in Table 1 are scaled by 10¹¹ for readability.

VI. CONCLUSIONS

This paper presents a compact PMOS-only reference voltage that employs CTAT/PTAT compensation and body-effect biasing to achieve high thermal stability and low power operation. By exploiting PMOS behavior in the triode region, a fine 1 mV trimmed resolution step from the range of 3.2 V to 4.2 V reference voltage, making the reference directly usable for ΔΣ-ADC-based BMS cell-voltage monitoring. The circuit achieves a temperature coefficient of 0.61 ppm/°C and maintains an output variation of 0.3 mV from -20°C to 100°C. The proposed design occupies a small area of 0.0038 mm² in 180 nm CMOS technology.