1. Advanced Compact MOSFET (ACM) Model

The ACM model supports accurate circuit design across all operation regions including weak, moderate, and strong inversion. This makes it suitable for circuits using MOSFETs in different regions at the same time. According to the ACM model, the drain current of a MOSFET is defined as the difference between the forward and reverse currents. The forward and reverse currents are further expressed as

where $i_f$, $i_r$, and $I_S$ are forward inversion level, reverse inversion level, and normalized current respectively. Forward inversion level is the degree of forward channel formation as influenced by the source voltage, and similarly, reverse inversion level is the degree of reverse channel formation under the influence of the drain voltage ^[6]. The normalized current $I_S$ is determined by the aspect ratio and the sheet-specific current $I_{SQ}$, as given in Eq. (2):

where $W$ and $L$ are width and length of a transistor, respectively. The $I_{SQ}$ is expressed in terms of the mobility $\mu$, oxide capacitance $C_{ox}$, subthreshold slope factor $n$, and thermal voltage $V_T$, as in Eq. (3):

As shown in Eq. (3), an $I_{SQ}$ is proportional to the square of the $V_T$. However, the carrier mobility exhibits an inverse temperature dependence with power of $m$. Given that $m$ is approximately 1.2, an $I_{SQ}$ exhibits a reasonably linear PTAT characteristic as shown in Eq. (4):

The relationship between source-drain voltages and current is given in Eq. (5).

$V_S$ is the source or drain voltage and $V_P$ is the pinch-off voltage described in Eq. (6):

where $V_{GB}$ and $V_{TH}$ are the gate-to-body voltage and the threshold voltage.

2. Conventional Structure

Fig. 1(a) illustrates a conventional MOSFET-only PTAT current generator, as presented in ^[4]. A PTAT voltage is developed across MN5 and MN6, operating in the weak inversion region. The structure composed of MN1, MN2, MP1, and MP2 ensures that the voltages $V_X$ and $V_Y$ are equal.

In Fig. 1(b), a self-cascode structure is depicted, which is employed in the MN3-MN4 and MN5-MN6 pairs shown in Fig. 1(a). Since M1 is a diode-connected MOSFET, its gate-to-drain voltage is equivalent to the gate-to-source voltage of M2. This configuration ensures that M1 operates in the saturation region. Consequently, M2 operates in the triode region. Based on these operating conditions, the output voltage of the self-cascode ($V_X$ in Fig. 1(b)) follows the relation:

where $S_1$ and $S_2$ represent the aspect ratios ($W/L$) of MN1 and MN2, respectively, and $N$ is the current mirror scaling factor. To ensure that $V_X$ is proportional to $V_T$, which is linearly dependent on temperature, the inversion level, $i_f$, must be much less than 1. This condition is satisfied when MN5 and MN6 operate in the weak inversion region ^[4]. Under this condition, Eq. (7) simplifies to:

Fig. 1. (a) Conventional MOSFET-only PTAT current generator ^[4] and (b) self-cascode structure ^[4].

In Fig. 1(a), the MN5-MN6 pair operates in the weak inversion region to generate a PTAT voltage at node $V_X$. Because $V_Y$ is equal to $V_X$, $V_Y$ also exhibits this PTAT behavior. This voltage is then applied to MN3, which operates in the triode region, effectively functioning as a resistor. The MN3-MN4 pair is designed to operate in moderate inversion to ensure that the voltage at $V_Y$ remains insensitive to current variations ^[4]. Further details regarding this mechanism will be discussed later in the paper. Since the PTAT voltage is applied to a resistor, a PTAT current is generated through MN3.

A discrepancy in the drain-to-source voltage ($V_{DS}$) across the MN1-MN2 and MP1-MP2 pairs degrades the PTAT current's line sensitivity. As the supply voltage (VDD) varies, these $V_{DS}$ differences also change. This is primarily due to channel length modulation (CLM) and drain-induced barrier lowering (DIBL), which cause variations in the currents of MN1 and MN2. The current mismatch leads to a voltage difference between $V_X$ and $V_Y$, which in turn affects nonlinearity of the PTAT current. To mitigate this issue, ^[5] adopts a cascode structure using MN7 and MN8 (Fig. 2). By biasing with the gate voltage of MN4, the drain voltages of MN1 and MN2 are equalized, improving line sensitivity. However, any mismatch between MN7 and MN8 leads to a mismatch in the $V_{DS}$ of MP1 and MP2. Therefore, further enhancement is necessary to fully suppress the challenge.

Fig. 2. MOSFET-only PTAT current generator with cascode structure ^[5].

3. Proposed Structure

To further improve the line sensitivity and reduce $V_{DS}$ mismatch, we proposed a MOSFET-only PTAT current generator, as shown in Fig. 3. The proposed structure incorporates a regulated cascode (RGC) configuration, which increases the output impedance ($R_{out}$). A higher $R_{out}$ results in minimized variations in $V_{DS}$ across the current mirrors (MN1-MN2 and MP1-MP2 pairs). Therefore, line sensitivity is significantly improved compared to prior works.

Fig. 3. Proposed MOSFET-only PTAT current generator incorporating a regulated cascode structure.

As shown in Fig. 3, MN8 and MP6 operate as a common-source amplifier. MN8 is biased by the current source MP5 which flows the same current of MP1 which biases MN1. To establish and maintain equal $V_{GS}$, MN8 is meticulously sized to match MN1. Given the unity (1:1) sizing ratios for both the MN1-MN2 and MP1-MP2 pairs, the $V_{GS}$ of MN2 is consequently identical to that of MN8. As MN2 is configured as a diode-connected MOSFET, its $V_{GS}$ is inherently equal to its $V_{DS}$. The circuit connectivity, where the drain of MN1 is coupled to the gate of MN8, ensures that the drain voltage of MN1 is equivalent to the $V_{GS}$ of MN8, which, by design, matches the $V_{GS}$ of MN2. This intricate setup is fundamental in guaranteeing $V_{DS,MN1} = V_{DS,MN2}$. In a parallel fashion, the identical dimensions of MP1, MP2, and MP6, combined with their forced equal drain currents, ensures $V_{DS,MP1} = V_{DS,MP2}$. MN7 and MP7 are cascode transistors that reduce the line sensitivity of the generated PTAT current by increasing the output impedance, aided by MN8 and MP6, which function as an amplifier.

Similar to the conventional PTAT generators shown in Figs. 1 and 2, the proposed PTAT current generator produces a PTAT voltage at $V_X$, which follows Eq. (9). To enhance line sensitivity, it is generally beneficial to increase $V_X$. However, it also raises the operating minimum VDD. To strike a balance, securing good line sensitivity while keeping the operating VDD lower, we have designed $V_X$ to be $2V_T$.

Since MP1, MP3, and MP5 carry the same amount of current, the current flowing through MN3 ($I_{D,MN3}$) is three times larger the current through MP1 ($I_{D,MP1}$). As described above, $I_{D,MN3}$ exhibits a PTAT characteristic. Consequently, $I_{D,MP1}$ also follows a PTAT behavior, and MP3, which is a current mirror of MP1, conducts a PTAT current ($I_{PTAT}$).

As previously discussed, MN5 and MN6 must operate in the weak inversion region, where the inversion factor ($i_f$) is less than 0.1, in order to generate a PTAT voltage at node $V_X$. The generated PTAT voltage becomes increasingly dependent on the parameter $\alpha$ in Eq. (8), rather than the bias current, as $i_f$ decreases. However, the inversion factor is highly sensitive to small changes in $V_X$, which can cause significant variations in the current ^[5]. To address this issue, MN3 and MN4 should be biased in the moderate inversion region, and the voltage generated by the MN3-MN4 self-cascode structure must be designed to match the PTAT voltage from MN5 and MN6. Since the current through MN3 and MN4 exhibits minimal change in $i_f$ even with variations in $V_X$, a stable PTAT current can be achieved ^[5]. Table 1 presents the transistor sizes used in the proposed design. The currents flowing through MP1, MP2, MP3, MP5, MP6, and MP8 are identical. However, MP4 carries approximately twice as much current as the others.

Since the proposed PTAT current generator employs positive feedback, a startup circuit is required to prevent the system from remaining in a zero-current state. We adopted a conventional startup topology similar to that presented in ^[5]. As shown in Fig. 3, the startup circuit consists of transistors MN10 - MN12, along with a capacitor $C_0$. During the power-up sequence, as VDD ramps from 0 to its nominal voltage, $V_{start}$ initially tracks VDD since $C_0$ is initially discharged. This behavior turns on MN11 which pulls down the gate voltage of MP1 ($V_{G,MP1}$). As $V_{G,MP1}$ decreases, the main PTAT circuit is moved out of the zero-current states, causing the drain voltage of MN2 to increase. Once MN1 turns on, it discharges the node $V_{start}$ through $C_0$ to ground, thereby turning MN11 off and terminating the startup sequence. Following the startup sequence, MN12 is activated, driving $V_{start}$ to ground. This action ensures that MN11 is reliably turned off, preventing it from affecting $V_{PG}$ once the main circuit is fully operational.

1. Simulation Results

Since the proposed PTAT current generator intended to improve the line sensitivity, the line sensitivity of various circuit structures in different process corners are compared in Fig. 4. Among the evaluated designs, the proposed RGC structure demonstrates the lowest line sensitivity in all the corners. It shows 0.14, 0.29, 0.09, 0.14 and 0.18 %/V at TT, FF, SS FS, SF corner, respectively. This result confirms that the $R_{OUT}$ enhancement provided by the RGC structure effectively improves line sensitivity, as previously discussed. Additionally, the simulated PSR at 10 Hz is -239.19 dB, when a 1 k$\Omega$ resistor is connected to the drain of the MP8 in Fig. 3.

Fig. 4. Comparison of line sensitivity across process corners for conventional ^[4], cascode ^[5], and the proposed design.

Fig. 5 presents the Monte Carlo simulation results of 500 samples for the temperature coefficient (TC) of the normalized current, simulated current divided by the mean value. The standard deviation of the TC over the temperature range from -20 $^\circ$C to 110 $^\circ$C is 0.124.

Fig. 5. Histogram of TC from post-layout Monte Carlo simulation (500 samples, TT corner, 1 V) over the temperature range of -20 $^\circ$C to 110 $^\circ$C.

Fig. 6. Simulation results of normalized IPTAT across process corners.

Fig. 6 illustrates the relationship between temperature and the normalized $I_{PTAT}$, referenced at 30 $^\circ$C, 78.47 nA, and the TT corner, across various process corners. All corners exhibit an R² value exceeding 0.99, indicating that the PTAT current exhibits a strong linear correlation with temperature.

2. Measurement

The proposed PTAT current generator was designed and fabricated using the Samsung 28-nm CMOS FD-SOI process. Fig. 7 shows the die photo of the proposed circuit. The circuit occupies an area of 239.89 $\mu$m $\times$ 124.38 $\mu$m, with a measured power consumption of 527.1 nW at 25 $^\circ$C. The measured power consumption was matched with expected value in the simulation results.

Fig. 7. Photo of the fabricated PTAT current generator.

The PTAT current generator is calibrated using a one-point calibration at 30 $^\circ$C and 1 V. This calibration point is chosen because 30 $^\circ$C is close to room temperature, and 1 V corresponds to the nominal supply voltage for the 28-nm process. The PTAT current was measured as the mean value of $I_{PTAT}$ in Fig. 3, while the $|V_{DS}|$ of MP8 varied from 0.5 V to 0.8 V. The normalized current is the measured current divided by measured current at 30 $^\circ$C of each sample die. The measured currents at 30 $^\circ$C are 75.3 nA, 83.6 nA, 56.1 nA, and 62.7 nA from each sample die.

Fig. 8. Measured line sensitivity.

Fig. 8 shows the PTAT current as a function of supply voltage. The PTAT current varies by less than 0.25% within the voltage range of 0.9 - 1 V, corresponding to a sensitivity of 0.25 %/V. These experimental results are higher than the simulation results, as the simulation did not account for device mismatches. Although the RGC suppresses the impact of device mismatches, the RGC gain is not infinite, and a gain error still exists. As a result, the gain error cannot fully suppress the line variation.

To demonstrate the linearity of the PTAT current generator, Fig. 9 presents the variation of the PTAT current with temperature. The measured data demonstrate excellent linearity, with R² values ranging from 0.9959 to 0.9980, showing close agreement with the simulation predictions. The results validate that the proposed PTAT current generator operates effectively with one-point calibration. Table 2 provides the specifications of the proposed PTAT current generator and comparison with several prior works.

Fig. 9. Measured PTAT current over temperature.