An FVF-based Capacitorless LDO with Segmented Power Cells Achieving Fast Transient
Response, Wideband High PSR, and Wide Load Current Range
JangDoojin1
-
(Cheongju University, Cheongju, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index terms
Low-dropout (LDO) regulator, flipped-voltage-follower (FVF), power-supply-rejection (PSR), capacitorless, segmented power cells
I. INTRODUCTION
Low-dropout (LDO) regulators are essential in modern power management for portable
electronics, IoT devices, and SoCs [1-4]. They provide stable power rails from unregulated sources with low voltage differentials,
crucial for circuit performance and battery life. However, achieving high PSR, fast
transient response, and wide load current range remains challenging, especially for
capacitorless architectures.
Many LDOs adopt flipped-voltage-follower (FVF) structures [5-9] for stability and transient advantages, particularly low output impedance for capacitorless
designs and fast feedback enabling fast load response. FVF-based LDOs incorporate
noise-cancelling transistors [8,9] to improve PSR for sensitive circuit blocks such as ADCs and clock generation circuits.
However, conventional FVF-based LDOs face challenges driving large power transistors
and maintaining performance across wide load ranges. Solutions like additional buffers
[6,7] introduce power consumption, area penalties, and stability issues. Stable bias points
across load variations remain problematic, causing performance degradation or requiring
complex compensation.
This letter proposes a segmented capacitorless LDO overcoming these limitations. The
LDO core implements multiple interconnected unit power cells, each with FVF structure,
noise-cancelling, and cascode transistors. This architecture extends driving capability,
enhances AC performance, and enables efficient on-chip power delivery through localized
distribution.
II. ANALYSIS OF PREVIOUS WORK
1. Advantages and Advancements in FVF-based LDOs
The key strength of FVF-based LDOs originates from the unique local feedback path
formed by the source follower, where any change in output voltage is immediately sensed
at the source node and reflected to the power transistor gate. This direct path creates
a low-impedance loop that quickly corrects output voltage deviations, making FVF highly
effective for capacitorless operation and rapid transient response [5-9]. A notable advancement [8] combines FVF structure with noise-cancelling transistors, improving PSR by directly
projecting input noise onto the power transistor gate (a diode-connected MMIR in Fig. 1(b)) while eliminating complex PSR enhancement circuitry.
Building on this, [9] incorporates adaptive biasing (implemented by a circuit with blue transistors in
Fig. 1(b)) to optimize wide-range load performance by dynamically adjusting tail current for
varying load conditions. The noise-cancelling transistor provides direct power transistor
driving, eliminating separate buffers [6,7] while enhancing PSR and maintaining bias margins across extended load ranges without
additional complexity.
Fig. 1. Existing FVF-based LDOs: (a) with a buffer at the power transistor gate [6,7], and (b) with a noise-cancelling transistor and an adaptive biasing circuit [9].
2. Persistent Challenges and Limitations of Conventional FVF LDOs
Despite advancements, conventional FVF-based LDOs face significant challenges. Some
implementations add buffers (shown in Fig. 1(a)) [6,7] to drive large power transistor gate capacitance, but buffers limit gate voltage
swing, constraining maximum load current while introducing power consumption, area
penalties, and potential stability issues.
A critical challenge involves bias point dependence on load current, particularly
with noise-cancelling transistors. Current mirror configuration between noise-cancelling
and power transistors makes source follower (MFVF in Fig. 1(b)) bias highly load-dependent. Load variations cause significant shifts in tail current
source (ITAIL) and source follower bias points, leading to excessive or insufficient bias current
flow. This creates large error amplifier (EA) output common-mode voltage variations,
potentially causing transient dips and output accuracy degradation.
Adaptive biasing circuits [9] attempting to decouple load current and bias correlation can inadvertently introduce
positive feedback loops, compromising stability under large load variations. These
limitations highlight the need for robust solutions addressing existing design constraints
while retaining FVF structure benefits with noise-cancelling transistors.
III. PROPOSED LDO ARCHITECTURE
The proposed capacitorless LDO overcomes conventional FVF-based challenges including
power transistor driving, wide-range performance, and bias stability. This work introduces
two major innovations over previous designs (e.g., Fig. 1):
1. Cascode Transistor Insertion and Fast Loop Performance
The proposed LDO incorporates a cascode transistor (labeled “Cascode Transistor” in
Fig. 2) into the fast loop to address the bias point variations that commonly degrade performance
in conventional FVF LDOs (distinct from the cascoded-FVF structure in [6], where the cascode stage mainly serves transient-enhancement purposes). By keeping
the cascode transistor in saturation, variations in the bias points of both the tail
current source (IB1) and the source follower (MF) are effectively minimized across a wide range of load conditions. This stabilization
not only prevents output common-mode voltage dips that can impair accuracy but also
avoids the positive feedback and bias fluctuations often introduced by adaptive bias
circuits.
Fig. 2. Top schematic of the proposed LDO with segmented power cells. A table of the
segment power cell design parameters is also included.
In normal operation, MF functions as a source follower driven by the EA’s output; however, during high-frequency
feedback events, fluctuations at VOUT propagate directly through MF’s source, causing MF to operate as a common-gate amplifier. The signal then passes through the cascode
transistor—also functioning as a common-gate amplifier—before driving the power transistor
(MP) configured in a common-source configuration, thereby forming a rapid response path
to stabilize VOUT. Because the fast path exhibits low impedances at each stage, the dominant poles
of the loop shift to higher frequencies, greatly widening the loop bandwidth. This
high-frequency pole placement simplifies stability requirements, reduces the need
for aggressive compensation, and allows bandwidth to be preserved without large passive
components. Consequently, the design achieves both fast transient response and a more
compact implementation.
2. Segmented Power Cell Architecture
The proposed LDO adopts a segmented architecture in which the core consists of multiple
interconnected unit power cells, each containing a power transistor, noise-cancelling
transistor (MM), cascode transistor, source follower, and current sources (IB1 and IB2). IB1 and IB2 are set to keep all devices in saturation across the cell’s full load range, with
IB2 providing supplementary bias even at 0 A load.
This segmentation offers substantial advantages in performance and flexibility:
-
Wide Load Range & High Slew Rate – Load capability is extended by dynamically enabling the required number of cells.
This allows efficient operation from light load to the 100 mA maximum in 65-nm CMOS.
Activating extra cells for large load steps further boosts slew rate for fast transient
recovery.
-
Predictive Control for Enhanced Efficiency and Transient Response – The segmented architecture’s dynamic cell enabling, indicated by the EN[N-1:0]
signals in Fig. 2, is proactively controlled by system-level commands, anticipating large load steps
to ensure fast transient recovery. This predictive scheme avoids stability issues
associated with complex adaptive biasing, while also reducing static current by disabling
unused cells, thereby improving overall power efficiency.
-
Efficient On-Chip Power Delivery – Distributed cell placement within an SoC shortens power routes, mitigating IR drop
and EM hot spots compared to centralized LDOs, and improving integration flexibility
as shown in Fig. 3.
Fig. 3. Addressing on-chip power delivery challenges (LDOs indicated by red hatched
areas): (a) limitations of centralized LDOs, and (b) mitigation through proposed segmented
LDO placement.
IV. SIMULATION RESULTS
The proposed LDO was implemented in 65-nm CMOS with 1.2-V input and 1.0-V output up
to 100 mA load current. Fig. 4 shows the chip layout, where 50 segmented power cells are arrayed in a compact form,
occupying an active area of 0.032 mm2. The segmented arrangement enables efficient layout utilization without significant
routing overhead despite multiple power-cell partitions.
Fig. 4. Layout of the proposed LDO with 50 segmented power cells.
Fig. 5 shows the AC responses of the slow and fast loops, with both loops maintaining stable
phase margins (> 49◦) across light (0 A) and heavy (100 mA) load conditions. The low-impedance
nodes in the fast loop push the dominant poles to higher frequencies, thereby widening
loop bandwidth and ensuring stability without complex compensation.
Fig. 5. AC simulation results: magnitude (in dB) and phase plots of (a) the slow loop
and (b) the fast loop under heavy (100 mA) and light (0 A) load conditions.
Fig. 6 shows that, up to 10 GHz, the simulated PSR’s worst-case (upper-envelope) value remains
< −14.2 dB for heavy (100 mA) and light (0 A) loads, demonstrating robust suppression
of supply ripple across load conditions. Transient behavior in Fig. 7 demonstrates a rapid response to a 30 mA load step with a 10 ns edge, with undershoot
and overshoot limited to 59 mV and 58 mV, respectively.
Fig. 6. Simulated PSR under heavy (100 mA) and light (0 A) loads.
Table 1 benchmarks the design against prior capacitorless LDOs. While previous works support
only 10–30 mA, the proposed LDO delivers 100 mA and exhibits a wideband PSR whose
worst-case value does not exceed −14.2 dB across the characterized band and load conditions,
together with fast transients, validating the effectiveness of the cascode-transistor
insertion and segmented architecture for stable, high-performance on-chip regulation.
Fig. 7. Simulated load transient response: (a) Waveforms of VOUT and the load step (0↔30 mA), and (b) undershoot and overshoot of VOUT.
Table 1. Performance comparison.
|
|
[5] |
[6] |
[9] |
[10] |
This work
|
|
Tech. [nm]
|
180
|
65
|
10
|
28
|
65
|
|
VIN [V]
|
0.7-1.1
|
1.05-1.2
|
1.8
|
1.2
|
1.2
|
|
VOUT [V]
|
0.6
|
0.9
|
0.95-1.75
|
1
|
1
|
|
IL,max [mA]
|
30
|
20
|
21
|
10
|
100
|
|
COUT [pF]
|
300
|
100
|
20
|
100000
|
100
|
|
*PSR [dB]
|
< -23 (fH = 10MHz)
|
< −3 (fH = 100MHz)
|
< −3 (fH = 10GHz)
|
< −37 (fH = 10GHz)
|
< −14.2 (fH = 10GHz)
|
|
Undershoot [mV] @ tr @ ΔIL
|
215@100ns@24mA
|
200@5ns @20mA
|
40@0.37ns @21mA
|
4.68@10ns @9mA
|
58@10ns @30mA
|
|
Area [mm2]
|
0.087
|
0.01
|
0.0061
|
NA
|
0.032
|
|
**FoM [ps]
|
1.02
|
0.65
|
0.897
|
1848
|
0.494
|
V. CONCLUSIONS
Conventional capacitorless FVF LDOs typically suffer from bias point variations and
limited performance over wide loads. This letter proposes an LDO with a cascode transistor
in the fast loop and segmented power cells, stabilizing bias points and enabling high
currents without complex compensation. Simulation results demonstrate stable operation
with > 49◦ phase margin, −14.2 dB peak PSR, and < 60 mV transient overshoot/undershoot
for 30 mA load steps, while supporting up to 100 mA load current. This approach offers
a scalable, robust solution for on-chip power regulation in advanced CMOS technologies.
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Doojin Jang received his B.S., M.S., and Ph.D. degrees in electrical and electronic
engineering from Kyungpook National University, GIST, and KAIST, South Korea, in 2010,
2014, and 2021, respectively. He worked for seven years at SK Hynix, LG Electronics,
and Samsung Electronics on semiconductor process technology, SoC design, and power-management
IP design, respectively. He is currently an Assistant Professor with the Department
of System Semiconductor Engineering, Cheongju University, South Korea. His research
interests include power-management circuits and integrated voltage regulators.