I. INTRODUCTION

In Internet of Things (IoT) applications, low-power, high-resolution analog-to-digital converters (ADCs) with moderate bandwidth are required. To meet these demands, successive approximation register (SAR) ADCs have been widely studied for their excellent performance and power efficiency ^[1,2]. Nevertheless, the improvement of the operating speed and the resolution of SAR ADCs is limited by the noise of comparators and the power consumption of the digital-to-analog converters (DACs).

Delta-Sigma (DS) ADCs can achieve high resolution by using oversampling and noise shaping techniques. However, DS ADCs have the disadvantage of limited bandwidth coming from high oversampling ratio (OSR). They also have relatively high power consumption. To address these issues, noise-shaping (NS) SAR ADCs have been proposed. The NS SAR ADCs combine the low power characteristics of the SAR ADC with the high resolution of the DS ADC ^[3-12].

To address the high static power consumption issue of OTAs in the loop filter ^[4], many previous studies have proposed using open-loop dynamic amplifiers ^[5,6]. However, these amplifiers are sensitive to variations in process, voltage, and temperature (PVT), causing gain variation that can adversely affect the noise transfer function (NTF). To avoid the use of these amplifiers, NS SAR ADCs employing passive integrators have been proposed ^[7,8]. A passive integrator using charge sharing can be designed using only two capacitors and a switch, offering the advantages of lower power consumption and insensitivity to PVT variations. However, passive integrators have severely lossy characteristics, which lead to weak NTFs.

However, the speed of NS SAR ADC is still limited by the serial nature of the SAR ADC operation, in which SAR ADCs convert bits one by one. Therefore, for an N-bit conversion, the comparator, the SAR logic circuit and the DAC should operate N times, which limits the speed. To address this issue, an NS SAR ADC incorporating a 2-bit/cycle structure was used in ^[3] to improve the conversion speed of the ADC. The 2-bit/cycle structure reduces the number of cycles, almost doubling the operating speed of the ADC ^[13,14].

In ^[3], for the noise shaping, an error-feedback (EF) structure using an open-loop dynamic amplifier was employed. However, the gain of the gain loop amplifier was sensitive to PVT variations, which can lead to degradation of NTF.

To overcome this problem, in this work, we propose a 2-bit/cycle second-order NS SAR ADC that combines an active integrator and a passive integrator in a cascade of integrators with feedforward (CIFF) structure. By using an active integrator in a closed-loop structure, we obtain robustness against PVT variations. To achieve the high open-loop gain required for the accuracy of the active integrator, the proposed ADC employs a floating inverter amplifier (FIA)-based ring amplifier (FBRA) ^[15,16]. The FBRA combines a high-gain, high-speed ring amplifier with the low power consumption characteristics of floating inverter amplifiers (FIAs). In ^[15] and ^[16], FBRA was employed to design a pipeline SAR ADC.

In this work, the passive integrator is employed to reduce power consumption, and the weak NTF problem is addressed by adjusting the gain ratio of multi-input pair comparators to achieve the desired NTF. The active integrator is used to integrate the residue voltage generated after the SAR conversion, and the passive integrator is used to integrate the output of the active integrator.

We demonstrate the performance of the proposed design implemented in a 28-nm CMOS process through SPICE-level simulations. When operated with a 1-V power supply, it achieves SNDR of 71 dB (ENOB $= 11.5$) at a sampling frequency of 400 MHz with the power consumption of 3.2 mW, leading to a Schreier figure of merit (FoM) of 172 dB.

The rest of this article is organized as follows. Section II presents the proposed 2-bit/cycle NS SAR ADC architecture, including its basic operation, and various non-idealities. Section III discusses the implementation of the proposed 2-bit/cycle NS SAR ADC. Section IV presents the SPICE-level simulation results and the performance summary. Finally, Section V concludes this paper.

II. PROPOSED 2-BIT/CYCLE NS SAR ADC

Fig. 1 shows the architecture of the proposed 2-bit/cycle NS SAR ADC. For simplicity, the architecture is shown as single-ended, but the actual circuit is differential. The proposed NS SAR ADC is composed of a sampling switch (S/H), two CDACs (REF-DAC and SIG-DAC), three multi-input comparators, and a loop filter consisting of an active and a passive integrator.

Fig. 1. Architecture of the proposed 2-bit/cycle NS SAR ADC.

Fig. 2. Timing diagram of the proposed 2-bit/cycle NS SAR ADC.

Fig. 2 shows the timing diagram of the proposed 2-bit/cycle NS SAR ADC. In the sampling phase (${\phi }_{CKS}$), the input voltage ($V_{IN}$) is sampled at the top-plate of the SIG-DAC using bootstrapped switches. After sampling, the SAR conversion is performed using ${\phi }_{CMP}$ and the residue voltage is produced. In the first integration phase (${\phi }_{\rm int1})$, the residue voltage in the SIG-DAC is used by the active integrator to generate $V_{\rm int1}$. In the second integration phase $({\phi }_{\rm int2})$, $V_{\rm int1}$ is integrated by the passive integrator to produce $V_{\rm int2}.$ ${\phi }_{\rm int2}$ is partially overlapped with the sampling phase for fast operation. Finally, in the reset phase (${\phi }_{RST})$, the dynamic integrator is reset.

Fig. 3. Operations of SIG-DAC and REF-DAC for the proposed 2-bit/cycle NS SAR.

Fig. 3 demonstrates the operations of SIG-DAC and REF-DAC for the proposed 2-bit/cycle NS SAR. The red line represents the sum of the SIG-DAC output and the two CIFF signals $\left(V_{\rm int1}\mathrm{,\ }V_{\rm int2}\right).$ The black line represents the reference voltages of $\pm V_{REF}$/2, $\pm V_{REF}$/8, $\pm V_{REF}$/32, or $\pm V_{REF}$/128 generated by REF-DAC for each conversion bit cycle. The three-input comparators compare the sum of the SIG-DAC output and the CIFF signals with the reference voltages and generate two-bit outputs (00, 01, 10, 11).

Fig. 4. Signal model of the proposed 2nd-order NS SAR ADC.

Fig. 4 shows the signal model of the proposed 2nd-order NS SAR ADC. In this model, the residue $V_{res}$ is derived by subtracting the final output $D_{\rm out}$ from the input sampling signal $V_{\rm in}$. The active integrator shown in the red box takes the residue voltage ($V_{res}$) as the input, and its output voltage ($V_{\rm int1})$ can be represented by

where $g_1={C_{SIG-DAC}}/{C_F}$ is the gain of the active integrator. The passive integrator, shown in the blue box, takes the $V_{\rm int1}$ as the input, and its output voltage ($V_{\rm int2}$) can be expressed by

where $b={C_{\rm int}}/{(C_{\rm int}+C_L)}$. Then, $V_{\rm int1}(z)$, $V_{\rm int2}(z)$ and $V_{\rm in}(z)$ are virtually summed by the three-input comparator. As observed from (2), the passive integrator has lossy characteristics. Therefore, we partially compensate this by adjusting the comparator gain ratio, $g_2$. From the signal model, the NTF of the proposed NS SAR ADC can be derived as follows:

which shows that the effect of the 2nd-order NS SAR ADC is achieved by using active and passive integrators.

As in ^[11], the coefficient ${b}$ is set to $3/4$ s a compromise between noise-shaping and stability. To determine $g_1$ and $g_2$, we performed MATLAB behavior simulations. Fig. 5 shows SNDR versus $g_1$ and $g_2$ obtained from the behavioral simulations. As $g_1$ and $g_2$ are increased, the SNDR is also increased. However, if we increase $g_1$ and $g_2$ excessively, we observe that the system becomes unstable and the SNDR drops rapidly. In the proposed ADC, based on the behavioral simulation results, we set $g_1$ at 1.4 and $g_2$ at 1.8.

Fig. 5. SNDR versus $g_1$ and $g_2$ from MATLAB behavioral simulations. (Average of 200 iterations, $V_{\mathrm{IN}=-0.9}$ dBFS).

Fig. 6. SNDR versus the open-loop gain from MATLAB behavioral simulations. (Average of 200 iterations, $V_{\mathrm{IN}=-0.9}$ dBFS).

Fig. 6 shows the SNDR versus the open-loop gain of the active integrator obtained from behavioral simulations. We can observe that the SNDR is about 78.6 dB with infinite open-loop gain. Even when the gain is reduced to 10 V/V, the SNDR reduction of the proposed NS SAR ADC is less than 1.5 dB. Considering the variation of the gain by PVT variation, we set the target gain at 30 V/V. The design of the amplifier used in the active integrator is covered in Section III.

Fig. 7. SNDR versus input-referred noise of comparators from MATLAB behavioral simulations. (Average of 200 iterations, $V_{\mathrm{IN}=-0.9}$ dBFS).

Fig. 7 shows SNDR versus the input-referred noise of the comparators from MATLAB behavioral simulations. The blue circles and red squares indicate the average of the SNDR and the worst 5% of the SNDR respectively. We assumed that the comparators have identical input-referred noise power. In Fig. 7, we observe that when the noise becomes larger than 1.5 mV${}_{\rm rms}$, the SNDR begins to drop rapidly. Therefore, it is determined that the comparator noise should be less than 1.5 mV${}_{\rm rms}$.

Since the proposed ADC structure requires three comparators, the offset mismatch between the comparators can degrade the performance. Fig. 8 shows the SNDR versus comparator input offset obtained from MATLAB behavioral simulations. The blue circles and red squares indicate the case where the offsets of the Comp1 and Comp3 in Fig. 1 move in the same direction, and the case where they move in opposite directions, respectively. Without loss generality, it was assumed that the offset of Comp2 was zero. Fig. 8 shows that the comparator offset should be limited to below several millivolts to maintain SQNR to be larger than 75 dB. Therefore, we decided to implement a comparator architecture with an extra input pair for offset calibration. The design of the offset calibration circuit is covered in Section III.

Fig. 8. SNDR versus comparators input offset from MATLAB behavioral simulations. (Average of 200 iterations, $V_{\mathrm{IN}=-0.9}$ dBFS).

III. CIRCUIT DESCRIPTION

1. FIA-based Ring Amplifier

As mentioned in the introduction, an accurate closed-loop active integrator requires an amplifier with a high open-loop gain. Recently, the use of FIAs for residue amplification in NS SAR ADCs has been introduced to minimize power consumption ^[17]. However, achieving both high gain and high speed with the existing structure is challenging. Conventional ring amplifiers are characterized by high gain and fast settling but have drawbacks such as energy inefficiency associated with the auto-zeroing mechanism and sensitivity to common-mode signals ^[18]. Therefore, for the active integrator, we used an FBRA to obtain high-speed and high gain. An FBRA combines the $V_{\rm CM}$ stability of a FIA with a ring amplifier with high-speed operation ^[15,16].

Fig. 9 shows the schematic of the active integrator using an FIA-based ring amplifier. When ${\phi }_{AMP} =$ Low, the reservoir capacitors $C_{R1}$(= 2.4 pF) and $C_{R2}$ ($= 1.3$ pF) are charged to $V_{DD} =1$ V, and the input and output of all of the three inverter stages reset to $V_{\rm CM} = 0.5$ V. This initialization ensures that the amplifier is in a fixed stable state before the amplification. When ${\phi }_{AMP}$ becomes high, the amplification starts. During this period, the discharge of $C_{R1}$ and $C_{R2}$ provides the amplifier with the necessary current to amplify the input. Since we employ an 8-bit ADC as the quantizer, the residue voltage at the input to the amplifier is within a few tens of millivolts.

Fig. 10 shows the gain of the designed FBRA as a function of the input voltage. When the differential input voltage changes from -10 mV to 10 mV, we can observe that the amplifier maintains a gain higher than 30, which ensures that the closed-loop integrator operates properly as shown in Section II with Fig. 6.

Fig. 9. Schematic of the FBRA.

Fig. 10. open-loop gain against input voltage from Spectre simulations. (typical corner).

Fig. 11. Simulated open-loop gain against V${}_{\rm CM}$ variations. (typical corner).

In the FBRA of Fig. 9, V${}_{\rm CM}$ was only used to reset the amplifier. Therefore, the FBRA operation should not be very sensitive to the variation of V${}_{\rm CM}$. To verify this, we repeated simulations while varying V${}_{\rm CM}$, and the results are shown in Fig. 11. We can observe that, even when the VCM changes by 10%, the gain is maintained over 34.

Because the proposed ADC uses open-loop amplifier architecture, the variation of the open-loop gain under process variation can be a concern. To verify the stable amplifier gain, we performed Monte-Carlo simulations. Fig. 12 shows the distribution of the open-loop gain of the designed FBRA due to process variations obtained from the Monte-Carlo simulations. Figs. 12(a) and 12(b) are for differential input of 2 mV and 30 mV, respectively. We observe that the open-loop gain of the amplifier is always greater than 30 V/V and satisfies the requirement on the open-loop gain.

Fig. 12. Simulated open-loop gain against process variations from Monte-Carlo simulations (1000 runs) (a) V${}_{\rm IN,diff} = 2$ mV, (b) V${}_{\rm IN,diff} = 30$ mV.

2. Offset Calibration

Fig. 13 shows the results of 200-run Monte-Carlo simulation of the comparator offset from mismatch at $27^\circ$C, $-40^\circ$C, and $85^\circ$C. We performed transient analysis with a slope input to analyze the comparator offset. We observe that the standard deviation of the offset is around 24 mV. As shown in Fig. 8, the offset of the comparators should be smaller than several millivolts to avoid severe SNDR degradation. Therefore, we implemented a comparator offset calibration circuit.

Fig. 14 shows the structure of the proposed foreground offset calibration circuit and the associated timing diagram. In addition to the input pairs for V${}_{\rm in}$, V${}_{\rm int1}$, and V${}_{\rm int2}$, the comparators have an additional input pair to receive the calibration signal V${}_{{\rm CAL}+(-)}$. The calibration is performed during ${\phi }_{FG}=high$. To determine the polarity of the offset, comparisons are performed with the main input pairs of the comparators connected to V${}_{\rm CM} = 0.5$ V (i.e., zero differential input).

Fig. 13. Simulated comparator offset variation against mismatch at $27^\circ$C, $-40^\circ$C, and $80^\circ$C from Monte-Carlo simulations (200 runs).

Fig. 14. Proposed offset calibration (a) structure and (b) timing diagram..

If the comparator output (CMP${}_{\rm out}$) is high, ${\phi }_{UP}$ becomes high, and ${\phi }_{DN}$ becomes low. This increases V${}_{{\rm CAL}+}$, while lowering V${}_{{\rm CAL}-}$. On the other hand, if CMP${}_{\rm out} =$ Low, V${}_{{\rm CAL}+}$ is lowered and V${}_{{\rm CAL}-}$ is elevated. This operation provides required negative feedback to control the differential calibration signal of V${}_{{\rm CAL}+} -$ V${}_{{\rm CAL}-}$. However, it cannot control the common mode of V${}_{{\rm CAL}+}$ and V${}_{{\rm CAL}-}$. To maintain the common mode near V${}_{\rm CM}$, C${}_{2+(-)}$ capacitors are used. In Fig. 14, when ${\phi }_{cal,1} =$ high, C${}_{2+(-)}$ are charged at V${}_{\rm CM}$. Subsequently, when ${\phi }_{cal,2}$ becomes high, the charge in C${}_{1+(-)}$ and C${}_{2+(-)}$ are shared, which moves V${}_{{\rm CAL}+}$ and V${}_{{\rm CAL}-}$ toward V${}_{\rm CM}$. It is noted that this charge sharing results in the leak of the differential calibration signal and limits its maximum value. The ratio C${}_{1}$/C${}_{2}$ should be determined considering this compromise between the efficiency of the differential operation and common mode stability. In our work, C${}_{1}$/C${}_{2} = 512$ was used.

Fig. 15. Waveforms showing the operation of the proposed offset calibration (V${}_{\rm os,diff} = 50$ mV).

Fig. 15 shows the waveform of V${}_{CAL+}$ and V${}_{CAL-}$ obtained from transient simulations. To artificially set up the comparator offset voltage for the simulation, a differential dc voltage of 50 mV was used. We observe that V${}_{CAL+}$ $\mathrm{-}$ V${}_{\rm CAL}$${}_{\mathrm{-}}$ grows from 0 until it saturates at 50 mV. The width of the waveforms in the figure represents the charge-injection from the turned-off switches.

Our foreground offset calibration scheme has its limitations. If the operating conditions change during normal operations, the V${}_{{\rm CAL}+}$ and V${}_{{\rm CAL}-}$ obtained from the foreground calibration will become less effective. However, we expect that the change of the offset after the foreground calibration will be limited. Furthermore, in principle, our calibration scheme can be applied in a background calibration, where the polarity of the offset is checked periodically during normal operation. However, it would inevitably slow down the ADC.

IV. SIMULATION RESULTS

The proposed 2-bit/cycle NS SAR ADC was implemented using a 28-nm CMOS process. It operates at the sampling rate of 400 MS/s with a 1-V power supply. With OSR of 8, this corresponds to 25 MHz of bandwidth.

Firstly, from transient noise simulations of the comparators, the input-referred noise of the comparator was determined to be 0.64 mV${}_{\rm rms}$ (data not shown). This result satisfies the design requirement of maintaining the comparator noise below 1.5 mV, as described in Fig. 7.

Fig. 16 shows the output spectrum of the proposed 2-bit/cycle NS SAR ADC obtained from Spectre simulations. The red and blue line represent the spectra from simulations without and with noise, respectively, and the vertical dashed line represents the bandwidth of 25 MHz. Noise simulations were performed using ``transient noise simulation'' of Spectre, with the noise model provided in the process design kit (PDK). The noise bandwidth ($f_{max,noise}$) of 100 GHz was used, which was determined to be high enough after iterations. We can clearly observe the characteristic of the 2nd-order noise shaping in both spectra.

Fig. 16. Output spectrum of the proposed ADC from Spectre transient simulations ($N_{fft}= 2048$, $V_{IN}=-0.9$ dBFS, $f_{sig} = 3.32$ MHz, $f_{max} = 100$ GHz). Red line: without noise, blue line: transient noise simulation.

Fig. 17 shows the SNDR versus input amplitude obtained from Spectre simulations. The blue circles and red rectangles represent the results of simulations with and without noise, respectively. When the noise was not included in the simulations, the maximum SNDR was 78.3~dB at an input amplitude of -0.9 dBFS. When the noise was included, the maximum SNDR was 71.0 dB and the resulting dynamic range was 73.1 dB.

Fig. 17. Input amplitude versus SNDR from Spectre transient simulations ($N_{fft} = 2048$, $f_{sig} = 3.32$ MHz, $f_{max} = 100$ GHz). Rectangles: with transient noise, circles: without noise.

Fig. 18. Input frequency versus SNDR from Spectre transient noise simulations ($N_{fft} = 2048$, $V_{IN} =-0.9$ dBFS, $f_{max} = 100$ GHz).

Fig. 18 shows the SNDR versus input frequency obtained from Spectre simulations at the input amplitude of -0.9 dBFS. There is little change in the SNDR performance when the input frequency is swept across the bandwidth of 25 MHz. The difference between the maximum and the minimum SNDR is less than 2 dB.

To confirm the robustness of the proposed ADC, we repeated transient noise simulations at multiple process variation corners and temperatures. Fig. 19 shows that the performance variation between corners is less than 1 dB. When the temperature changes from $-40^\circ$C and $85^\circ$C, the SNDR variation was slightly larger but is still limited to around 2 dB. These results show that the designed ADC is robust against process and temperature variation.

Fig. 19. SNDR variation versus temperature and each corner condition from Spectre transient noise simulations ($N_{fft} = 2048$, $V_{IN}=-0.9$ dBFS, $f_{max} = 100$ GHz).

When operated with the sampling rate of 400 MS/s with 1-V supply voltage, the proposed 2-bit/cycle NS SAR ADC consumes 3.2 mW, where 0.6 mW, 0.68 mW, and 0.86 mW are consumed by the integrator, the comparators, and the C-DACs, respectively. The power consumption of the main components is shown in Table 1.

The Schreier FoM is 172 dB and the Walden FoM is 22.1~fJ/conv-step. The performance of the proposed NS SAR ADC is summarized and compared with those from the previous works in Table 2. We observe that the proposed ADC has similar performance with the previous works. It is noted, however, that the performance numbers of the proposed work are from simulations and that of the existing works are from measurements except those of ^[15].

V. CONCLUSION

This paper presents a 2-bit/cycle second-order NS SAR ADC employing a multi-bit cycle structure. The multi-bit/cycle structure allows for high-speed operation. The second-order noise shaping, realized through a CIFF structure, achieves both high gain and high-speed operation using the FBRA while minimizing power consumption. We employed a combination of active and passive integrators as a compromise between power consumption and robustness against PVT variation. In addition, the proposed NS SAR ADC is designed with an offset calibration circuit to address the offset issues in the structure using three comparators. As a result, we designed a high performance, high energy-efficient NS SAR ADC with the Schreier figure of merit (FoMs) of 172 dB.