I. INTRODUCTION

With the recent aggressive scaling and performance improvements in CMOS Technology, more Terahertz integrated circuits in CMOS have been reported ^[1-5]. Two Schottky barrier junction diodes (SBDs) in CMOS, shallow trench separated (STS-) and poly gate separated (PGS-) SBD, have been introduced relatively recently ^[6,7]. Since the SBDs have an excellent high-frequency performance with the cut-off frequency above 1 THz, it has been employed in various millimeter-wave and sub-terahertz CMOS circuits ^[8-11].

The Schottky junction of the STS- and PGS-SBD is defined (separated) using Shallow Trench Insulator (STI) and poly-gate-separator, respectively. An STS- and PGS-SBD with the cut-off frequency of 1.5 and 2.0 THz has been achieved, respectively ^[6,7]. The STS-SBD has a lower cut-off frequency due to its higher series resistance (The current path is longer by the embedded STI separator) ^[12].

The Schottky junction exhibit a large leakage current due to its low barrier height and sharp electrode edge effect ^[13]. The junction edge of STS-SBD is surrounded by the STI isolator while that of PGS-SBD is directly open to an n-well. The PGS-SBD experiences more than 10X higher leakage current in a reverse bias region in spite of the superior RF characteristic ^[14].

The electrically-floating poly-gate-separator in the PGS-SBD defines a Schottky junction region ^[7,15]. This paper proposes a novel PGS-SBD with improved DC or RF performance by biasing the poly-gate-separator in the PGS-SBD. The accumulation channel under the poly-gate separator enhances the leakage current characteristic or cut-off frequency depending on the bias voltage applied to it.

Section II describes the proposed device structure and TCAD simulation results. Section III shows the measurement results of DC and RF characteristics of biased PGS-SBD. Section IV summaries the paper with conclusions.

II. DEVICE STRUCTURE

Fig. 1 shows the cross-section of the biased PGS-SBD. The Schottky diode junction is formed (surrounded) by a poly-gate (gate), which is connected to the bias voltage (V${}_{\rm g}$). It is different from the previous PGS-SBD, where the poly-gate-separator is electrically floating ^[12]. V${}_{\rm d}$ and J${}_{\rm d}$ represents an applied diode voltage (across the anode and cathode) and its corresponding diode current density, respectively. V${}_{\rm g}$ represents the voltage across the gate and cathode.

Fig. 2 shows the layout of the biased PSB-SBD. The structure is similar to a standard CMOS transistor except a source or drain is replaced with a Schottky junction (anode). The design parameters are L${}_{\rm g} = 120$ nm, L${}_{\rm j} = 40$ nm, and W${}_{\rm f} = 6.4$ $\mu$m. A multi-finger configuration with the number of finger (N${}_{\rm f}$) of 8 is employed. The total Schottky junction area is 2.56 $\mu$m${}^{2}$ (L${}_{\rm j} \times$ W${}_{\rm f} \times$N${}_{\rm f}$). The previous floating-gate STS- or PGS-SBDs employed a square ring type poly-separator to maximize the cut-off frequency ^[6,13]. Yet the proposed device employs the conventional multi-finger configuration of standard MOS transistors.

TCAD (Silvaco) simulations are conducted to investigate operation principles of the biased PGS-SBD ^[16]. The doping concentration of the n-well is set to ${\sim}10^{17}$/cm${}^{3}$ for the simulations. The models used for the device simulations were CVT, SRH and FERMI. Fig. 3 show the current density in the cross-section of the single-cell device for varying V${}_{\rm g}$'s under a forward bias (V${}_{\rm d} = +1.0$ V). The poly-gate on the n-well structure is similar to an accumulation-mode MOSCAP varactor ^[17]. The depletion regions are formed (around the anode) when a negative V${}_{\rm g}$ ($-1. 0$ V) is applied (Fig. 3(a)). The current flows around the depletion region through the n-well region, which increases the series resistance of the device. An accumulation channel is formed as V${}_{\rm g}$ increases above 0 V (Fig. 3(c)). Fig. 3(b) shows the current density when the gate is grounded (V${}_{\rm g} = 0$ V). Most current flow through the channel beneath the gate, which decreases the series resistance of the device.

Fig. 1. Cross-section of the biased PGS-SBD.

Fig. 2. Layout of the biased PGS-SBD.

Fig. 3. Simulated current density of the biased PGS-SBD using TCAD for (a) V$_{\rm g} = -1.0$ V, (b) V${}_{\rm g} = 0$ V, and (c) V${}_{\rm g} = +1.0$ V. V${}_{\rm d} = +1.0$ V for all cases.

III. MEASUREMENT RESULTS

1. DC Characterization

The device is fabricated in a 130-nm CMOS process without any process modification. The size of the test structure is 200$\times$180 $\mu$m${}^{2}$ (Fig. 4). The DC characteristics of the device are measured using a semiconductor parameter analyzer. Figs. 5(a) and 5(b) shows the measured diode current densities (J${}_{\rm d}$) versus diode voltages (V${}_{\rm d}$) for varying gate voltages (V${}_{\rm g}$) in a linear and log scale, respectively. A higher J${}_{\rm d}$ is observed for a higher V${}_{\rm g}$ in the forward bias region, which is consistent with the TCAD simulation results. Fig. 6 shows the forward diode current density versus V${}_{\rm g}$ of the biased PGS-SDB. J${}_{\rm d}$ increases by 42% (from 1.00 to 1.42 mA/$\mu$m${}^{2}$) for V${}_{\rm d} = +1.0$ V as V${}_{\rm g}$ changes from $-1$ V to $+1$ V. The current density of the floating gate is slightly higher than that of V${}_{\rm g} = 0$ V.

Fig. 7 shows the measured leakage current densities of the diode under reverse bias voltages. J${}_{\rm d}$ reduces by $\sim$10X (from $2.4 \times 10^{-5}$ to $2.1 \times 10^{-6}$ mA/$\mu$m${}^{2}$) for V${}_{\rm d} = -1.0$ V as V${}_{\rm g}$ changes from $+1$ V to $-1$ V. This phenomenon can be explained by the formation of depletion regions at the edge of the Schottky junction to reduce the leakage current under the reverse bias voltage (Fig. 3(a)).

The forward and leakage current characteristic has been improved by $\sim$10% (V${}_{\rm d} = +1.0$ V) and $\sim$5X (V${}_{\rm d} = -1.0$ V), respectively, versus that of the floating-gate PGS-SBD by tuning the poly-gate voltage (V${}_{\rm g}$). There are no major changes of the basic structure of the floating-gate PGS-SBD.

Table 1 shows the diode parameters of the biased PGS-SBD at the zero gate voltage (V${}_{\rm g} = 0$ V). The parameters are calculated using the equations in ^[15].

Fig. 4. Die photograph of the fabricated test structure.

Fig. 5. Measured J-V curve of the biased PGS-SBD in (a) linear scale and (b) log scale.

Fig. 6. Measured forward current density (J$_{\rm d}$) versus gate voltage (V$_{\rm g}$) of the biased PGS-SDB.

Fig. 7. Measured leakage current density of the biased PGS-SDB versus the gate voltage (Vg) in the reverse bias region.

Table 1. Diode parameters of the biased PGS-SDB.

Parameter	Value
Ideality factor	1.21
Saturation current density (mA/mm2)	2.5×10-7
Zero-bias Schottky barrier height (V)	0.49
Turn-on voltage (V)	0.35

2. RF Characterization

Fig. 8 shows the measured series resistance (R${}_{S}$) and zero-bias junction capacitances (C${}_{\rm j0}$), which are extracted from measured S-parameters using a vector network analyzer and GS RF probe ^[6]. The measured R${}_{\rm S}$ decreases by 44% (from 25.5 to 14.4 ohm) due to the formation of the accumulation channel as expected. C${}_{\rm j0}$ slightly increases by 7% (from 8.32 to 8.87 fF) as V${}_{\rm g}$ increases. The parameters at V${}_{\rm g}$ = 0 V are close to those of the floating-gate.

Fig. 9 shows the calculated cut-off frequency ($1/($R${}_{\rm S}\cdot$C${}_{\rm j0}$)) using the data in Fig. 8. The cut-off frequency increases by 67 % as V${}_{\rm g}$ increases (from 0.75 to 1.25 THz). The cut-off frequency at V${}_{\rm g} = +1$ V is 34% higher than that of the floating-gate PGS-SBD (0.93 vs 1.25 THz).

Table 2 compares the performance of SBDs in CMOS. The biased PGS-SBD shows cut-off frequency compared to other highly optimized SBDs ^[7,15]. The leakage current is better than that of STS-SBD at V${}_{\rm g} = -1$ V ^[6]. The device has comparable or better performances to other CMOS SBDs without design optimizations. A proper bias voltage needs to be selected depending on the operation modes (either a forward or reverse bias region) of applications.

Fig. 8. Measured Series resistance (R$_{\rm S}$) and zero-bias junction capacitance (C$_{\rm j0}$) versus the gate voltage (V$_{\rm g}$).

Fig. 9. Cut-off frequency versus the gate voltage (V$_{\rm g}$).

Table 2. Performance summary of SBDs in CMOS.

Ref.	Forward current (mA/mm2) @ Vd=+0.4V	Leakage current (nA/mm2) @ Vd=-0.4V	Cut-off frequency (THz)
[6]	15	10	1.5
[7,14]	86	78	2.0
[15]	8.7	87	1.3
This work (Vg=+1V)	86	23	1.25
This work (Vg=-1V)	5.3	2.1	0.75

IV. CONCLUSIONS

A novel PGS-SBD was proposed, fabricated and measured. The biased PGS-SBD device achieved considerable improvement in either the leakage current ($\mathrm{\sim}$5X) or cut-off frequency (34%) versus the floating-gate PGS-SBD by controlling the gate bias voltage. Since no design optimization is made for the biased PSG-SBD, the performances would be further improved with design optimizations.