I. INTRODUCTION

The bidirectional neural interface has been the subject of extensive research for the diagnosis and treatment of neurological and psychiatric diseases such as epilepsy and seizures ^[1-10]. In the case of a typical neural recorder, the following factors need to be considered during the design process. First, it must be designed for low power consumption. Neural recorders are often configured with multiple channels, and if excessive power is consumed, it could lead to tissue damage. Thus, to operate several dozen to hundreds of channels simultaneously, limited amount of power in the micro-watt range may be allocated for each amplifier. Another important consideration is the need for low-noise performance. The desired signals exist in the range of tens of $\mu$V to several mV in amplitude and within the frequency band of 1 Hz to 10 kHz. To capture these input signals, both high gain and low noise performance are essential. Typically, neural recorders require input reference noise performance in the range of 5 to 10 $\mu$V$_{\rm rms}$ in the 1 Hz to 10 kHz frequency band ^[1].

The bidirectional neural interface consists primarily of a neural recorder and a neural stimulator. In order for the stimulator to deliver sufficient amount of current to the high impedance electrode-tissue interface, the output voltage of the neural stimulator can be quite large, ranging from a few volts to tens of volts. This output voltage can result in significant stimulation artifacts through the cerebrospinal fluid (CSF) via direct conduction pathways, which can appear as large artifacts in the recorder ^[2-8]. Specifically, CM artifacts can reach up to 450-600 mV${}_{\rm PP}$, while DM artifacts can range from 45 to 60 mV${}_{\rm PP}$ ^[3]. As a result, the neural recorder may become saturated and fail to operate correctly. Therefore, bidirectional neural interfaces must be designed to tolerate such stimulation artifacts. Reference ^[4] categorizes artifact removal methods into four main approaches: filtering, template subtraction, overdesign, and blanking. Each method has its pros and cons and should be designed based on the specific characteristics. The filtering method requires high-order low-pass filters to reduce the harmonic frequencies of stimulation artifacts, making it unsuitable for detecting higher-frequency spike signals ^[5]. The template subtraction method requires pre-learning of stimulation artifacts before the artifacts can be removed in the subsequent front-end input ^[6]. The blanking method involves blocking and disabling the recorder when the stimulator operates, which results in signal loss during the blocking moments ^[7]. The overdesign method records both stimulation artifacts and neural noise floor simultaneously, aiming to remove the artifacts during post-processing ^[3,8]. Generally, in analog front-ends where neural amplifiers are placed, a high-gain amplifier is positioned at the front and a low-resolution ADC at the back to reduce the overall power consumption of the circuit. However, in the overdesign method, the neural recorder places a low-gain amplifier with a wide operating range to record even the artifacts, and a high-resolution ADC is used at the back end ^[8], which raises the design complexity of the ADC.

This study proposes a neural recording amplifier utilizing adaptive gain control and a feedback-based common mode cancellation loop (CMCL), which operates at maximum gain and excellent noise performance under normal conditions. In cases where artifacts occur, it can remove the CM components and, if necessary, lower the gain before the amplifier saturates, thereby extending the amplifier's dynamic range (DR).

The structure of this paper is as follows. Section II explains the main circuit design of the proposed neural amplifier in detail, while Section III presents the post-layout simulation results and compares them with previous similar works. Finally, Section IV concludes the paper.

II. CIRCUIT DESIGN

Fig. 1 shows the block diagram of the proposed neural recording amplifier circuit. The proposed circuit can be broadly divided into two main parts: the AC-coupled capacitive-feedback low-noise amplifier (LNA) with adaptive gain control, which dominates the overall noise performance of the circuit, and the common mode rejection unit, which includes the feedback-based CMCL.

The LNA is designed as a two-stage transconductance amplifier consisting of G${}_{\rm m1}$ and G${}_{\rm m2}$, and it consumes 78% of the total power used by the entire circuit for low noise characteristics. Fig. 2(a) shows the circuit diagram of G${}_{\rm m1}$, which uses an inverter-based OTA with a current reuse technique, a structure known for its good noise performance ^[9,10,12]. For G${}_{\rm m2}$, shown in Fig. 2(b), a 5-transistor fully differential OTA structure is used to ensure an adequate output range. The gain of the LNA is adjusted by controlling the feedback capacitor value through an envelope detector, four comparators, and a digital logic circuit.

The common mode rejection unit consists of the traditional CMCL circuit and an additional unit to control the on/off state of the CMCL. The CMCL is a feedback-based structure that uses a current mirror structure (A${}_{\rm CM}$), and the CMCL on/off control unit detects the common mode (CM) components coming into the LNA input, compares the size of the detected CM components, and adjusts the switch on/off through a digital logic circuit.

Fig. 1. Overall simplified structure of the proposed neural recording amplifier.

Fig. 2. Schematic of (a) G${}_{\rm m1}$ (b) G${}_{\rm m2}$.

1. Adaptive Gain Control LNA

Fig. 3 shows the adaptive gain control LNA constructed with a cross-coupled feedback capacitor. The LNA is designed with a maximum gain of 40 dB to capture small neural signals. With such a high gain, if large differential artifacts ranging from a few mV to several tens of mV are introduced at the input, the output will quickly saturate. The proposed LNA maintains a gain of 40 dB under normal conditions, but if the amplified output suddenly increases and reaches a certain threshold, the gain will be reduced by one step. After the output amplitude decreases and the envelope falls below a specific threshold after a certain period, the gain will return to the original 40 dB. The gain adjustment process occurs in four stages: 40 dB, 26.02 dB, 20.92 dB, and 17.72 dB.

Fig. 4 presents the circuit diagram of the envelope detector, designed based on a cross-coupled differential-driven rectifier structure ^[11]. This block is designed to automatically adjust the LNA's gain and determine when to return to the original state. The envelope follows the rapid rise of the LNA output, and once the output stabilizes at a lower gain level, the envelope drops accordingly. This allows the system to return to the original gain when the signal level is sufficiently maintained.

Fig. 5 illustrates the gain adjustment decision block, which consists of four comparators, three SR latches, and several logic gates. The PEAK signal from the envelope detector is compared with two thresholds, DM_Limit_P (800 mV) and DM_safe_P (520 mV), to determine the gain adjustment operation based on the comparison results.

Fig. 3. Schematic of the proposed adaptive gain control LNA.

Fig. 4. Schematic of envelope detector.

Fig. 5. Schematic of gain control logic unit.

2. Common-mode cancellation unit

Fig. 6 shows the components of the common-mode cancellation unit. It consists of the CMCL circuit that removes CM artifacts and the circuitry that detects the magnitude of the CM components entering the input and controls the on/off state of the CMCL. The CM artifacts that enter the LNA input operate as a source follower and appear at the source terminal of the input transistor. This CM signal is inputted to the CMCL amplifier (A${}_{\rm CM}$) through the S${}_{np}$ terminal, and its output is fed back to the input of G${}_{\rm m1}$. As a result, the input of G${}_{\rm m1}$ operates as a negative feedback loop from the CM signal perspective, leaving only the error signal at the input of G${}_{\rm m1}$ ^[13,14]. If the output of the A${}_{\rm CM}$ amplifier does not saturate, it can be expressed as follows:

(1)

$ \left(E_{\rm CM}\frac{C_{IN}}{C_{\rm Acm}}+V_{\rm Acm}\right)\left(\frac{C_{\rm Acm}}{C_{\rm Acm}+C_{IN}}\right)=V_{Gm1,in}, $

where the output of the A${}_{\rm CM}$ amplifier, V${}_{\rm Acm}$, is given by

(2)

$ V_{\rm Acm}=-E_{\rm CM}\cdot \frac{C_{in}}{C_{\rm Acm}}. $

In this case, the CM components at the input of G${}_{\rm m1}$ are reduced to the error component, which approaches zero. The CMCL effectively removes the CM component that negatively affect the neural recorder. However, due to the presence of C${}_{\rm Acm}$, the input-referred noise (IRN) performance may deteriorate. Therefore, when the CMCL is unnecessary, a MOS switch is used to break the loop, improving the noise performance ^[13].

Fig. 7(a) shows the circuit diagram of the amplifier that detects CM components entering the neural recorder, and Fig. 7(b) shows its small-signal equivalent circuit. By applying Kirchhoff's current law (KCL) at the V${}_{\rm CM,sense}$ node, we derive the following equation:

(3)

$ V_{o1}+V_{o2}=2\left(1+\frac{C_1}{C_2}\right)\cdot V_{\rm CM,sense}-\frac{2C_1}{C_2}\cdot E_{\rm CM}. $

At node V${}_{1}$, the small-signal analysis yields

(4)

$ V_1=\frac{\left(1+g_mr_{on}+\frac{C_1}{C_2}\right){\cdot V}_{\rm CM,sense}-\frac{C_1}{C_2}{\cdot E}_{\rm CM}}{1+g_mr_{on}}. $

From the output terminals V${}_{o1}$ and V${}_{o2}$, the following equation is derived

(5)

$\left(sC_2+\frac{1}{r_{op}}+\frac{1}{r_{on}}\right)\left(\frac{V_{o1}+V_{o2}}{2}\right)+\left(g_m-sC_2\right)\cdot V_{\rm CM,sense}\nonumber\\ =\frac{1+g_mr_{on}}{r_{on}}\cdot V_1. $

By substituting (3) and (4) into (5), we get

(6)

$ V_{\rm CM,sense}=\frac{sC_1C_2r_{op}+C_1}{sC_1C_2r_{op}+C_1+C_2}\cdot E_{\rm CM}. $

Since sC${}_{1}$C${}_{2}$r${}_{op}$ is much smaller compared to C${}_{1}$ and C${}_{2}$, it can be approximated as zero, simplifying to

(7)

$ V_{\rm CM,sense}\approx \frac{C_1}{C_1+C_2}\cdot E_{\rm CM}. $

The V${}_{CM_sense}$ signal is then used to control the switch of the CMCL through a comparator and logic circuit.

This switch-based on/off control of the CMCL has the advantage of removing CM artifacts when the switch is on, while providing excellent noise performance when the switch is off. However, this switching behavior can cause a change in the amplifier's bandwidth. To address this, the circuit is designed to maintain a constant bandwidth of Sub 1 Hz to 10 kHz, even when the CMCL is engaged, by reducing the compensation capacitor during the switching operation ^[13].

Fig. 6. Schematic of CMCL control logic unit.

Fig. 7. CM sensing amplifier (a) schematic and (b) small-signal equivalent model.

III. POST-LAYOUT SIMULATION RESULTS

The proposed IC is designed using a 0.18-$\mu$m CMOS process, and Fig. 8 shows the layout of the entire neural recorder, which occupies a total area of 0.36mm${}^{2}$, including an on-chip unity gain buffer for testing purposes.

Fig. 9 presents the AC simulation results for the proposed LNA at various gain levels. The LNA can adjust its gain from the typical 40 dB down to a minimum of 17.72 dB. Table 1 lists the total harmonic distortion (THD) of the LNA's output when large differential signals are input at a fixed gain. The adaptive gain control LNA automatically lowers its gain when large differential signals lead to higher THD, thus increasing the differential input range. At a 17.72 dB gain, the LNA maintains a THD of less than 1% even with a 77 mV${}_{\rm PP}$ differential input.

Fig. 10 illustrates the transient simulation results of the proposed amplifier. In Fig. 10(a), the LNA input is a 1 kHz frequency signal that increases by 1 mV${}_{\rm PP}$ every 2 ms, reaching a maximum of 77 mV${}_{\rm PP}$ before settling at 1 mV${}_{\rm PP}$. Fig. 10(b) shows that the LNA automatically reduces its gain by one step before saturation and distortion occur. The envelope signal of the LNA output triggers gain control when it exceeds a certain threshold (800 mV). Fig. 10(c) shows the waveform where the gain automatically returns to 40 dB after the differential input decreases. As the differential signal decreases, the envelope signal gradually drops below a threshold (520 mV), and the gain is restored to its original value.

Fig. 8. Layout of proposed neural recording amplifier.

Fig. 9. Simulated AC response.

Fig. 10. Simulated transient results (a) LNA differential input signal (max. 77 mV${}_{\rm PP}$) (b) LNA differential output (c) gain control operation (17.72 dB to 40 dB).

Fig. 11 shows the maximum and minimum output values of the envelope detector circuit in response to differential inputs at a frequency of 1 kHz. For small inputs below 200 mV${}_{\rm PP}$, the output peak does not fully track the input amplitude; however, it still functions properly for detecting the 800 mV threshold. And when the differential input amplitude is less than 75 mV${}_{\rm PP}$, the minimum output drops below 520 mV. In this case, if the LNA gain is lower than 40 dB, it returns back to 40 dB.

Fig. 11. Envelope detector output voltage versus input voltage.

Fig. 12 shows ths input noise simulation results of the LNA based on the on/off operation of the CMCL. The IRN in the 1 Hz -- 10 kHz range is 2.32 $\mu$V${}_{\rm rms}$ when CMCL is off and 3.57 $\mu$V${}_{\rm rms}$ with CMCL on. In the worst-case scenario, with a 17.72 dB gain, the IRN is 2.59 $\mu$V${}_{\rm rms}$ with CMCL off and 3.75 $\mu$V${}_{\rm rms}$ with CMCL on.

Fig. 12. Simulated input referred noise with CMCL ON/OFF.

Fig. 13 presents the voltage spectrum simulation results of the amplifier output when a 4 mV${}_{\rm PP}$, 1 kHz differential input signal and a 1 V${}_{\rm PP}$, 50 Hz CM signal are applied. Due to the CMCL, the CM component is effectively eliminated, with a $-51.7$ dB difference between the fundamental and third harmonic components, resulting in a THD of 0.418%.

Fig. 13. imulated output voltage spectrum with CM artifact.

Fig. 14 presents the CMRR simulation results of the proposed neural amplifier, showing a performance of over 89 dB in the signal frequency band and 115 dB near DC.

Fig. 14. Simulated CMRR of proposed amplifier.

Fig. 15. Overall power consumption of the proposed circuit.

Fig. 15 illustrates the overall power consumption of the proposed circuit. To achieve low noise performance, the LNA is allocated 1.56 $\mu$W of power, which accounts for 78% of the total power consumption of 2 $\mu$W.

Table 2 compares the key performance metrics of the proposed amplifier with other existing studies. Thanks to the flexible gain control, the proposed neural amplifier can operate with high gain in ideal conditions and extend the differential input range (up to 77 mV${}_{\rm PP}$) through gain control in specific situations. This enables the use of a lower-resolution ADC at the backend, thereby reducing the overall power consumption of the system. In general, the noise efficiency factor (NEF) and power efficiency factor (PEF) are commonly used to evaluate the noise-power trade-off performance of neural signal recording amplifiers ^[14]. When compared with previous works using a figure of merit (FoM) that also takes silicon area into account, the proposed design achieves a FoM below 1.35, demonstrating excellent overall efficiency. At the same time, it maintains a THD of less than 1% even with a 1 V$_{\rm PP}$ CM input.

IV. CONCLUSION

The proposed neural recording amplifier with adaptive gain control and common-mode cancellation loop is designed using a 180 nm CMOS process and maintains a THD of less than 1% at 1 V${}_{\rm PP}$ of CM artifacts. The circuit maintains a gain of 40 dB under ideal conditions and, in the presence of artifacts, automatically controls the CMCL on/off based on the magnitude of incoming CM components. Simultaneously, it reduces the gain to a maximum of 17.72 dB before the output saturates due to differential-mode (DM) artifacts, preserving linearity. Under ideal conditions, the circuit demonstrates an IRN performance of 2.32 $\mu$V${}_{\rm rms}$ in the 1 Hz -- 10 kHz bandwidth.