I. Introduction

With the rapid advancement of integrated circuits, the gate oxide breakdown voltage and operating voltage of transistors are progressively decreasing. This trend has resulted in a narrowing electrostatic discharge (ESD) design window ^[1,2,3]. Gate-grounded MOSFET (GGNMOS) is commonly utilized as ESD protection device due to its uncomplicated device structure and excellent process compatibility ^[4,5,6]. However, due to its triggering mechanism and the layout structure of multi-finger GGNMOS, the traditional multi-finger GGNMOS faces the problem of uneven current conduction ^[7]. In addition, the trigger voltage of traditional GGNMOS devices is generally about 10V, while in 3.3 V I/O protection applications, the minimum breakdown voltage of gate oxide of MOS devices is 9V, which requires the trigger voltage of ESD protection devices to be lower than 9V. These issues have hindered the widespread adoption of traditional GGNMOS for 3.3 V I/O ^[8].

The uneven current conduction phenomenon in traditional multi-finger GGNMOS is attributed to the fact that the parasitic NPN of the central finger is located far from the substrate protection ring, resulting in a higher parasitic resistance of the substrate, which will trigger before side fingers and bear ESD stress alone. The substrate self-triggering technology utilizes the central finger current of the earliest conduction in traditional GGNMOS as the substrate trigger current to conduct other fingers. This method effectively improves the uneven conduction of GGNMOS ^[9,10]. Zhang proposed a GGNMOS embedded with an additional diode ^[11]. The diode was embedded near the cathode substrate ring of GGNMOS, and the trigger voltage could be adjusted by altering the distance between N$+$ and P$+$ of the diode. By controlling the breakdown voltage (BV) of the additional diode, the diode is initially triggered to supply the substrate current for GGNMOS, thus addressing uneven current conduction issues in multi-finger GGNMOS. However, using additional diodes can only reduce trigger voltage to about 9 V, which remains high for 3.3 V I/O. Further reduction may lead to increased leakage current due to proximity between heavily doped regions N$+$ and P$+$ ^[12,13]. Dynamic substrate resistance technology represents an effective approach to alleviating the uneven current conduction phenomenon in GGNMOS. In this technique, an NW is added between the source of the side finger of the traditional GGNMOS and the cathode substrate P$+$ ring, and it is connected to the device anode through N$+$. When an ESD event occurs, the potential of the N-well rises, lengthening the current transmission path and indirectly increasing the substrate resistance, which facilitates the uniform turn-on of the device. However, the device still has a relatively high trigger voltage, rendering it unsuitable for low-voltage applications of 3.3 V. To reduce the triggering voltage of GGNMOS, Sun proposed a GGNMOS triggered by an embedded PNP structure. In this design, P$+$ implantation and an N-well are embedded in the drain of the central finger of the traditional GGNMOS, forming a vertical PNP. The base of the PNP is connected to VDD. When the emitter voltage of the PNP exceeds the base voltage by 0.7 V, the PNP turns on and provides substrate current for the GGNMOS ^[14]. Ma proposed a GGNMOS triggered by an external PMOS. The gate of the PMOS is connected to VDD, and the PMOS with a lower trigger voltage turns on first to supply substrate current for the GGNMOS. Both of these devices have reduced the trigger voltage and enabled the uniform turn-on of GGNMOS by providing substrate current. Nevertheless, to achieve a lower trigger voltage, these devices all need to be connected to the VDD power bus to receive control signals, which undoubtedly increases the complexity of metal wiring ^[15].

In this paper, a floating-bulk NMOS triggered GGNMOS (FBTGGNMOS) is proposed. Based on the standard 0.18um CMOS process, the FBTGGNMOS can achieve a relatively low trigger voltage without the need for additional detection circuits and control signals. FBTGGNMOS utilizes floating-bulk NMOS as its triggering structure, the BV of floating-bulk NMOS is expected lower than traditional GGNMOS. And the addition of the floating-bulk NMOS structure effectively reduces the triggering voltage and improves the current conduction uniformity of traditional GGNMOS. This enhancement allows the structure to meet the requirements of 3.3V I/O.

II. Device structure and operating mechanism

2.1 Structure and operating mechanism of FBTGGNMOS

The cross-section and equivalent circuit diagram of the traditional GGNMOS are depicted in Fig. 1. When ESD current is applied to the anode of GGNMOS, the avalanche breakdown occurs at the collector junction of QNPN1, QNPN2, QNPN3, the avalanche current flows through the P-well into cathode, creating a voltage drop on the P-well parasitic resistance RPW. Since the central finger is furthest from the substrate protection ring, QNPN1 is the first to reach 0.7 V, QNPN1 turns on, bears ESD stress alone. The obvious disadvantage of this turn-on mechanism is if the central finger QNPN 1 fails before the other fingers are turned on, fingers of the GGNMOS could not be fully conducted and the failure current $I_{t2}$ will be very low. And the BV of the collector junction of traditional GGNMOS is generally around 9V, which will result in the trigger voltage of GGNMOS is too high to be applied to ESD protection in 3.3 V I/O.

To reduce the triggering voltage of GGNMOS and improve the uneven current conduction phenomenon, FBTGGNMOS is designed. The layout and cross-section of the proposed FBTGGNMOS are depicted in Fig. 2.

The FBTGGNMOS consists of ``GGNMOS'' and ``floating-bulk NMOS''. The GGNMOS section is a traditional multi-finger GGNMOS. The newly added floating-bulk NMOS serves as the trigger structure of the device and is located in the middle of the device. Floating-bulk NMOS constitutes an isolation ring (ISO-Ring) through the newly added NW and DNW to isolate the P-well of floating-bulk NMOS and P-SUB, so that the bulk potential is floating. The gate and source of floating-bulk NMOS is grounded. The source is connected to another highly doped region p+-tab in the device through a metal wire, the p$+$-tab is located near the PW-ring of the GGNMOS cathode and provides the triggering current for the GGNMOS.

When ESD current is applied to the anode of FBTGGNMOS, the collector junctions of floating-bulk NMOS and GGNMOS are in a reverse bias state, different from the triggering mechanism of traditional GGNMOS, the BV of floating-bulk NMOS is expected lower than GGNMOS. Therefore, the collector junction reverse bias diode of floating-bulk NMOS takes the lead in avalanche breakdown, generating electron-hole pairs, the triggering current flows from the source end of floating-bulk NMOS to p+-tab through the metal wire, and then flows into the cathode through the P-well, forming a triggering path as shown by the red line in Fig. 2(b). The triggering current generates a voltage drop on the equivalent resistance of the P-well, the multi-fingered GGNMOS around the floating-bulk NMOS begin to conduct, releasing ESD currents.

Fig. 1. (a) Cross-section view and (b) equivalent circuit diagram of traditional GGNMOS.

Fig. 2. (a) Layout, (b) cross-section view, and (c) equivalent circuit diagram of FBTGGNMOS.

2.2 BV analysis of FBTGGNMOS and traditional GGNMOS

The primary design consideration for FBTGGNMOS is to ensure that the floating-bulk NMOS exhibits a lower BV than the GGNMOS, enabling it to be activated first to supply the triggering current for GGNMOS. Fig. 2(c) illustrates this phenomenon, Q1 is the parasitic NPN of floating-bulk NMOS; Q2 is the parasitic NPN of GGNMOS, RPW is P-well parasitic resistor.

In order to better analyze the BV difference between Q1 and Q2, their equivalent circuit model is shown in Fig. 3. The voltage added by VCE is the device anode. Q2 is shown in Fig. 3(c), there is a resistor RPW between the base and the emitter, while the GGNMOS shown in Fig. 3(a) does not, but its floating base can be regarded as a resistor $R\to \infty$,which is shown in Fig. 3(b), obviously $R\gg R_{\rm PW}$. In this way, Q1 has the same circuit topology as Q2, the only difference between them is the resistance between the emitter and the base.

According to literature ^[16,17], in the common emitter connection, the conditions for avalanche breakdown are

(1)

$\alpha M=1, \nonumber$

$ M=\frac{1}{\alpha} $

Avalanche multiplication factor M can be given by empirical formula

(2)

$ M=\frac{1}{1-\left(\frac{V_{\rm CE}}{V_{\rm B}}\right)^{S}} $

$V_{\rm B}$ is the avalanche breakdown voltage of collector PN junction, $S$ is the empirical constant, between 3-6. From formula (1), it can be concluded that

(3)

$\frac{1}{\alpha} =\frac{1}{1-\left(\frac{V_{\rm CE}}{V_{\rm B}}\right)^{S}}$

$ V_{\rm CE}=V_{\rm B}\sqrt[S]{1-\alpha} $

So $V_{\rm CE}$ is the BV of Q1 and Q2, the main difference between Q1 and Q2 is the size of the resistance. For the Q2 depicted in Fig. 3(b), RPW plays a shunt role here, and the current flowing through RPW is the majority carrier current in the base region, which does not contribute to the collector current. This part of the holes in the base region flows to the cathode of the device through the P-well parasitic resistance, which will increase the barrier height of the emitter junction and reduce the electrons diffused to the base, which reduces the injection efficiency of the transistor. For Q2 in Fig. 3(b), the resistance R in the same position is much larger than RPW and tends to infinity, where electrons cannot be shunt, so Q2's transistor injection efficiency $\alpha$ is higher than Q1, according to the formula (3), Q2 has a lower BV than Q1.

Fig. 3. Parasitic NPN circuit diagram of (a), (b) floating-bulk NMOS (Q1) and (c) GGNMOS (Q2).

III. Simulation and discussion

To understand the operational mechanism of FBTGGNMOS, technology computer-aided design (TCAD) software is used to conduct simulation of FBTGGNMOS. Fig. 4 shows the impact ionization distribution of FBTGGNMOS and traditional GGNMOS under a 3.8 V DC voltage bias. Which is different from GGNMOS, stronger impact ionization was observed near the drain N+ and P-well junction of floating-bulk NMOS in FBTGGNMOS, the results indicated that the floating-bulk NMOS was the first to induce avalanche breakdown.

To further investigate the working process of the device, a transient pulse (10ns rise time,100ns pulse width) signal with an amplitude of 0.5A is applied to the anode of FBTGGNMOS. The current density distribution of FBTGGNMOS during the initial conduction period is shown in Fig. 5(a). A significant current is observed in the floating-bulk NMOS, with its bulk potential measured at 1.07 V, whereas the bulk potential of GGNMOS is approximately 0.3 V. This observation suggests that the parasitic NPN transistor of the floating-bulk NMOS was activated first, thereby establishing the trigger path as depicted by the red line. This phenomenon is attributed to the significantly lower breakdown voltage of the floating-bulk NMOS in comparison to that of the central finger of GGNMOS, resulting in the activation of floating-bulk NMOS prior to GGNMOS.

The triggering current generated by floating-bulk NMOS is injected into GGNMOS by P+-tab and then transferred into the device cathode through the P-well parasitic resistance, which increases the base potential of the side finger of GGNMOS. As illustrated in Fig. 5(b), when the central finger of the GGNMOS reaches a voltage of 0.73 V, the side finger simultaneously rises to 0.75 V. This observation indicates that the trigger path enhances the activating capability of the side finger to match that of the central finger. Consequently, all parasitic NPN within FBTGGNMOS are activated simultaneously, effectively mitigating the risk of premature device failure due to the early conduction of any individual finger. And Fig. 5(c) shows the current path when all fingers are fully turned on to release the high ESD current. The floating-bulk NMOS functioning as the trigger is still capable of discharging ESD current, indicating that this portion of the increased area is utilized effectively.

Fig. 4. Impact ionization rate distributions of (a) FBTGGNMOS and (b) traditional GGNMOS under 3.8 V voltage bias.

Fig. 5. Current density distribution of FBTGGNMOS when (a) floating-bulk NMOS turns on, (b) side finger turns on, and (c) complete conduction.

IV. Experimental results and discussion

GGNMOS and FBTGGNMOS were designed and implemented based on 0.18 um CMOS process. GGNMOS is 32 fingers, FBTGGNMOS is a 32 fingers GGNMOS with 2 fingers floating-bulk NMOS.For comparison and verification, the finger length is both 50 $\mu$m, and the same source-drain width and channel width are used.

Fig. 6 illustrates the breakdown voltage (BV) comparison between traditional GGNMOS and FBTGGNMOS. The BV of traditional GGNMOS is 8.8 V, whereas the BV of FBTGGNMOS triggered by floating-bulk NMOS is significantly lower at only 4.2 V, exceeding the operating voltage of 3.3 V, a phenomenon attributed to the specific characteristics of floating-bulk NMOS previously discussed.

The performance of the proposed FBTGGNMOS is evidently superior to that of the traditional GGNMOS. The triggering voltage of FBTGGNMOS is 3.68V (41%) lower than that of the traditional GGNMOS, only 5.24 V. This indicates that the added floating-bulk NMOS triggering structure works successfully, which significantly reduces the triggering voltage of the device. As can be seen from the enlarged diagram near the holding voltage point in Fig. 7, The TLP I/V curve of FBTGGNMOS, represented by the red line, demonstrates a smoother trend near the holding voltage point, whereas the GGNMOS, depicted by the blue curve, demonstrates significant fluctuations. This is because the traditional GGNMOS is turned on by the central finger with larger substrate resistance first, and then other fingers conduct slowly and irregularly, as a result, this leads to irregular fluctuations in the curve. And FBTGGNMOS is triggered by floating-bulk NMOS to help the side finger, which is more difficult to turn on, so that the device conducts more evenly, and the curve is smoother. The curves of FBTGGNMOS and GGNMOS after the holding voltage point almost coincide, and the $I_{\rm t2}$ of FBTGGNMOS is 12.64 A, 1.4 A higher than that of the traditional GGNMOS. This is attributed to the fact that, on the one hand, the current distribution in FBTGGNMOS is more uniform, which mitigates the risk of localized overheating and enhances the failure current. On the other hand, floating-bulk NMOS is triggered in advance before the GGNMOS section is subjected to excessive current. This reduces the heat accumulation rate of the GGNMOS part and improves the overall device stability. Although their conduction characteristics are similar, the temperature of the GGNMOS section in FBTGGNMOS during initial operation is lower than that in traditional GGNMOS, consequently, conventional GGNMOS tend to reach the failure threshold more rapidly.

Figure of merit (FOM) is defined to evaluate the overall performance in terms of effective ESD robustness, layout area and the capability of reducing the trigger voltage

Experimental results are listed in Table 1, the data presented in the table indicates that the triggering effect of FBTGGNMOS is notable in reducing the triggering voltage; however, its area is also augmented. Nevertheless, since floating-bulk NMOS is still capable of discharging ESD current after its triggering task is completed, the area efficiency ($I_{\rm t2}$/Area) of FBTGGNMOS is only reduced by 0.1 compared with that of GGNMOS. The FOM of FBTGGNMOS is significantly higher than that of GGNMOS. It can thus be concluded that the FBTGGNMOS using the floating-bulk NMOS triggering can effectively reduce the triggering voltage of GGNMOS and still maintain high robustness.

Fig. 8 depicts the 1 ns VF-TLP (100 ps rise time, 1 ns pulse width) results of FBTGGNMOS and GGNMOS. In comparison to GGNMOS, the IV curve of FBTGGNMOS exhibits a leftward shift. During rapid ESD events, the triggering voltage of GGNMOS reaches 12.3 V. Nevertheless, the trigger voltage of FBTGGNMOS remains notably low, measured at 4.74 V, and the dynamic on-resistance is similar to GGNMOS. Fig. 9 shows the transient voltage waveform of FBTGGNMOS and GGNMOS under a 60V pre-charge voltage. It can be seen that the overshoot voltage of GGNMOS is close to 10 V, which cannot provide effective protection. The overshoot voltage of FBTGGNMOS is significantly lower than that of GGNMOS, only about 6 V, and the clamping voltage of FBTGGNMOS is also significantly lower than that of GGNMOS, which proves that FBTGGNMOS has better performance during fast ESD events.

Fig. 7 shows the test results of GGNMOS and FBTGGNMOS using the transmission line pulse (TLP) tester (10 ns rise time, 100 ns pulse width).

Fig. 6. The breakdown voltage measurement results of GGNMOS and FBTGGNMOS.

Fig. 7.

Fig. 8. 1 ns VF-TLP measurement results of FBTGGNMOS and GGNMOS.

Fig. 9. 1 ns VF-TLP measurement results of FBTGGNMOS and GGNMOS under 60 V pre-charge voltage.

V. Conclusion

In this paper, a floating-bulk NMOS triggered GGNMOS(FBTGGNMOS) is proposed and successfully implemented based on 0.18 $\mu$m CMOS process. TCAD simulation results show that when ESD events come, the added floating-bulk NMOS conduct firstly to provide triggering current for GGNMOS and help the device to conduct evenly. The reason for the low BV of floating-bulk NMOS is analyzed. TLP test results show that compared with traditional GGNMOS, the triggering voltage of FBTGGNMOS is reduced by 41%, only 5.24 V. The holding voltage attains 4.42 V, exceeding $3.3$ V$+10$% safety margin. The VF-TLP test results indicate that the proposed FBTGGNMOS is capable of managing fast ESD events. With low triggering voltage, high holding voltage, high robustness, the proposed FBTGGNMOS can meet the requirements of ESD protection for 3.3 V I/O protection applications.