I. INTRODUCTION

Three-Dimensional (3D) NAND flash memory technology is at the forefront of contemporary data storage innovations, characterized by vertically stacked layers composed of silicon dioxide (SiO${}_{2}$) and tungsten layers. In the fabrication process of 3D NAND flash memory, an oxide layer initially serves as a spacer, followed by the stacking of a sacrificial nitride layer. The sacrificial layer is then replaced with tungsten derived from silicon nitride (Si${}_{3}$N${}_{4}$) to establish the polysilicon channel ^[1]. The key step in this process involves the precise etching of the oxide-nitride (ON) stack layer to facilitate channel formation. However, increasing the number of cells by stacking the ON stack has reached a limit due to issues with the hole etching technique, specifically plasma etching technology ^[2,3]. Therefore, efforts to increase the number of cells without additional stacking continue. One such research direction explores the possibility of doubling the cell count by splitting cells without stacking. In a previous study, cells were fabricated with the intention of splitting, which resulted in differing characteristics in twin cells due to misalignment during registration ^[4]. This misalignment caused two cells to exhibit variations in operational characteristics, with one showing an increase in current and the other a decrease. Consequently, substantial differences in the attributes of the two cells emerged, posing challenges to assessing the uniformity of cell properties. Previous work suggested that dividing cells through slit cuts in a hemi-cylindrical (HC) structure resulted in a 2.5 times higher integration density compared to the conventional gate-all-around (GAA) structure. Based on these findings, we focused on the HC 3D NAND flash ^[5]. In this study, we introduce a pioneering approach that aims to achieve identical characteristics in the split cells by employing selective etching technique as the primary approach. Through this process, the split cells are fabricated with the same characteristics on both sides. This work suggests a device using the technology computer-aided design (TCAD) simulation package, Sentaurus Sprocess, to validate the proposed integrated processing scheme and to verify the identicality in device characteristics of the split cells.

II. PROCESS INTEGRATION

The process flow for precise division of split cells based on 3D NAND technology is depicted in Fig. 1(a) through (e). Fig. 1(a) refers to the Silicon (Si) wafer. Fig. 1(b) illustrates the formation of the ON stack via deposition on a Si substrate ^[6,7]. The number of ON stacks determines the number of cells within the 3D NAND architecture. The ON pitch is set to 50 nm ^[8], with three layers stacked consecutively. Hole etching is performed using plasma etching ^[9,10], forming a string with gate-all-around (GAA) cells through the hole etching. Sequentially, the blocking oxide/Si${}_{3}$N${}_{4}$ charge trap layer/tunneling oxide (O/N/O) and the channel can be deposited into the hole using low-pressure chemical vapor deposition (LPCVD) ^{[11,12,13,14]}. After each deposition step, the structure is flattened using chemical-mechanical polishing (CMP) ^[15].

Here, the core process is explained as follows: After channel deposition, the oxide gap fill process is performed by ALD forming the buried oxide (BOX) generates small holes ^[16], as shown in Fig. 1(c). These generated holes are used for alignment, and a cylindrical plasma etch is performed as shown in Fig. 1(d). The plasma etch at this point is the same method used during the initial hole etch process. After this cylindrical plasma etch, a part of the BOX remains and the other part of the channel opens due to the elliptical cell shape. The remaining BOX that can be referred as sidewall spacers is used as oxide masks for the selective etching to divide the cells. In order to etch the channel, a selective wet and dry etching processes with tetramethylammonium hydroxide (TMAH) can be adopted to remove the poly-Si ^[17,18]. Subsequently, HF is applied for the selective wet and dry etching of SiO${}_{2}$ to remove the thin tunneling oxide ^[19,20]. The sidewall spacers are etched during this process. The Si${}_{3}$N${}_{4}$ is etched through a selective wet etching process using H${}_{3}$PO${}_{4}$ ^[21,22]. Following these steps, the structure comes into a shape in Fig. 1(e). The inner oxide is then filled, and CMP is performed. Slit etching replaces the Si${}_{3}$N${}_{4}$ layers on the ON stack with W to form the gate and distinguish strings ^[23,24]. After the slit etching at the individual string level, the Si${}_{3}$N${}_{4}$ layer is removed by H${}_{3}$PO${}_{4}$ solution to facilitate W gate deposition and subsequent etch-back processing, shaping the 3D NAND flash memory as shown in Fig. 1(f). The originally connected W gate due to deposition processing is separated into dual gates by the etch-back processing. Reaching at this stage, finally the back-end-of-the-line (BEOL) is completed.

Fig. 1. Schematic of the process integration. (a) Si substrate. (b) ON stack deposition. (c) buried oxide (BOX) gap fill. (d) side wall spacer processing by plasma etching. (e) split cell construction by selective etch and (f) W replacement.

III. STRUCTURE OF A UNIT FLASH CELL

The final 3D structure of a unit flash cell, presumably fabricated using the Sentaurus Sprocess, is illustrated in Fig. 2. It simulates the stacking of three ON stacks based on the proposed process flow. For the comparative analysis of the split cells, they can be designated by `cell_left' and `cell_right' in the following analysis results. The gate and sidewall spacer materials are W and SiO${}_{2}$, respectively, as figured out in the previous section, with both layers having lengths of 25 nm. The thicknesses are as follows: the blocking oxide layer is 6 nm, the Si${}_{3}$N${}_{4}$ charge trap layer is 5 nm, the tunneling oxide is 3 nm, and the channel has a thickness of 5 nm. The nonlocal tunneling model was applied to confirm the characteristics of the split cells during program and erase operations, with higher accuracy and credibility. While pursuing higher integration density, the increasing number of ON stacks might cause the array to have tilting inside the high aspect-ratio hole during hole etching, rather than achieving an exactly cylindrical geometry. A practical solution was proposed in previous literature to either differentiate the program/erase (P/E) voltages or adjust the channel doping profile between the top cell and the bottom one to match the threshold voltage (V${}_{\rm TH}$) ^[25].

Fig. 2. Device structure schemed by TCAD Sentaurus.

IV. SIMULATION RESULTS

As shown in Fig. 3(a), incremental step pulse programming (ISPP) is performed with voltage increasing from 10 V to 22 V with 2 V increment over total 7 pulses. Each program pulse is applied for $2\times10 ^{-5}$ s. As shown in Fig. 3(b), incremental step pulse erasing (ISPE) is conducted with voltage decreasing from -14 V down to -26 V with -2-V decrement, encompassing a total of 7 pulses. Each erase pulse is applied for $4\times10 ^{-5}$ s. Fig. 3(c) shows the V${}_{\rm TH}$ shift obtained by ISPP, with V${}_{\rm pass}$ of 6 V. As identified in the figure, the ISPP slope of cell_left is 0.65 V/V and that of cell-right is also 0.65 V/V, which assures that the split cells have been presumably fabricated by the process simulation. Fig. 3(d) shows the V${}_{\rm TH}$ shift by ISPE. The ISPE slopes for cell_left and cell_right are 0.42 and 0.41, respectively, showing a high consistency, which again affirms the matched behaviors of the split cells. Fig. 4 shows the cell current (I${}_{\rm cell}$) as a function of gate voltage V${}_{\rm GS}$. The transfer characteristics were observed over the range from -4 V to 12 V for a programmed cell (program voltage = 16 V) and I${}_{\rm cell}$ is measured at V${}_{\rm GS} = 10$ V. I${}_{\rm cell_left}$ and I${}_{\rm cell_right}$ are $7.82\times 10 ^{-5}$ A and $7.80\times 10^{-5}$ A, respectively, which reveals that the I${}_{\rm cell}$ characteristics of the split cells show no practical difference and confirms the identicality.

The transient change in V${}_{\rm TH}$ and I${}_{\rm cell}$ are shown in Fig. 5(a). In Fig. 5(a), it is observed that $\Delta$V${}_{\rm TH}$ for cell_left and cell_right are 1.09 V and 1.08 V, respectively. Also, $\Delta$I${}_{\rm cell}$ for cell_left and cell_right are depicted to be both $2.8\times 10 ^{-7}$ A. Fig. 5(b) shows the change in the amount of charge of electrons trapped after program and retention operation. The program voltage was 14 V and applied for $1\times 10^{-4}$ s. The data retention and graphical analysis on charge redistribution were observed after $1\times 10^{3}$ s at 300 K. These results consistently indicate that there is no distinction in retention characteristics between the split cells.

Fig. 3. P/E characteristics. (a) ISPP and (b) ISPE schemes. V${}_{\rm TH}$ shifts over the (a) ISPP and (b) ISPE operations.

Fig. 4. Comparison between the I${}_{\rm D}$-V${}_{\rm GS}$ characteristics of cell_right and cell_left.

Fig. 5. Retention characteristics at different cell locations. Transient changes in (a) V${}_{\rm TH}$ and I${}_{\rm cell}$ and (b) amount of electron charges after program and retention operation.

V. CONCLUSION

In this work, we presented a novel process integration to enhance the cell density and match the device characteristics of the split cells in the 3D NAND flash memory. The proposed process integration creates a sidewall spacer oxide mask through the holes generated during the BOX gap filling. Using a selective etch process, the channel, tunneling oxide, charge-trap layer, and blocking oxide are sequentially divided in half. Over the sequences, the capability to create self-aligned cells using selective material etching has been proven. Furthermore, the proposed approach is substantiated through TCAD simulations, and a comprehensive analysis of these paired split cells reveals strikingly similar characteristics in terms of I${}_{\rm cell}$, V${}_{\rm TH}$ shifts by ISPP and ISPE, and retention characteristics. Therefore, the viability of the proposed process integration for a novel 3D NAND flash memory having higher integration density has been confirmed.