| Title |
Digital-memory Hybrid Counter-based SRAM In-memory Computing |
| Authors |
(Siyeol Lee) ; (Dasom Ahn) ; (Sung Hun Jin) ; (Taehui Na) |
| DOI |
https://doi.org/10.5573/JSTS.2026.26.3.181 |
| Keywords |
Binary neural network (BNN); counter; deep learning; energy efficiency; in-memory computing (IMC); low power; MAC; memory wall; MRAM; SRAM; scalable exponent counter (scalable EC) |
| Abstract |
To address the bottleneck caused by the memory wall in conventional computing systems, in-memory computing (IMC) has gained significant research interest. While the digital approach to IMC can achieve high accuracy, its energy efficiency is often lower than that of analog IMC approaches. To address this limitation, the Ternary-output Binary Neural Network-based IMC (ToBNN-IMC) has gained attention. ToBNN-IMC can achieve both high accuracy and energy efficiency through its digital nature and the use of a zero-skipping technique. However, ToBNN-IMC has been experienced only with STT-MRAM memory macro. Moreover, its accumulating strategy, which counts multiplication results using a counter with a fixed bit-width, can suffer from degraded accuracy when the number of multiply-accumulate (MAC) operations exceeds the counter’s range. To overcome this issue, the proposed digital-memory hybrid counter-based SRAM IMC (hybrid SRAM-IMC) employs a counter design referred to as the scalable exponent counter, which enables accurate accumulation and direct extraction of neuron activation regardless of the number of MAC operations. By implementing this design, the hybrid SRAM-IMC achieved 96.58% inference accuracy on the MNIST dataset, 88.64% on the CIFAR-10 dataset, and 94.00% on the SVHN dataset, demonstrating accurate MAC operation without any accuracy loss, regardless of the number of accumulations. |