| Title |
An 85.7 TOPS/W Analog-digital Combined In-memory Computing Accelerator for Mixed-precision Deep Neural Networks |
| Authors |
(Byeongcheol Kim) ; (Wooyoung Jo) ; (Sangjin Kim) ; (Soyeon Um) ; (Hoi-Jun Yoo) |
| DOI |
https://doi.org/10.5573/JSTS.2025.25.4.346 |
| Keywords |
Computing-in-memory; mixed-mode computing; mixed-precision; energy-efficient; AI accelerator |
| Abstract |
This paper introduces a novel computing-in-memory (CIM) processor designed for processing deep neural networks (DNNs) with mixed precision, overcoming the limitations of previous CIM architectures that employed bit-serial operations for multi-bit data. The proposed solution, termed the mixed-mode mixed-precision CIM (mixed-CIM) processor, integrates two main features for enhanced energy efficiency: first, the mixed-CIM architecture, which improves energy efficiency by 55.5% compared to prior approaches; second, a digital CIM approach for in-memory multiply-and-accumulate (MAC) operations that boosts throughput by 41.3%. The processor, developed using 28 nm CMOS technology with an area of 1.96 mm2 , achieves an energy efficiency of 85.7 TOPS/W while maintaining 77.4% accuracy on CIFAR100 with ResNet18. |